Datasheet

301
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
28.6 Boundary-scan Related Register in I/O Memory
28.6.1 MCUCR – MCU Control Register
The MCU Control Register contains control bits for general MCU functions.
• Bits 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG
interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence
must be followed when changing this bit: The application software must write this bit to the desired value twice
within four cycles to change its value. Note that this bit must not be altered when using the On-chip Debug system.
28.6.2 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction
AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
28.7 ATmega640/1280/1281/2560/2561 Boundary-scan Order
Table 28-1 on page 302 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected
as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-
out order as far as possible. Therefore, the bits of Port A and Port K is scanned in the opposite bit order of the other
ports. Exceptions from the rules are the Scan chains for the analog circuits, which constitute the most significant
bits of the scan chain regardless of which physical pin they are connected to. In Figure 28-3 on page 299, PXn.
Data corresponds to FF0, PXn. Control corresponds to FF1, PXn. Bit 4, bit 5, bit 6 and bit 7 of Port F is not in the
scan chain, since these pins constitute the TAP pins when the JTAG is enabled.
28.8 Boundary-scan Description Language Files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format
used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register
are included in this description. BSDL files are available for ATmega1281/2561 and ATmega640/1280/2560.
Bit 76543210
0x35 (0x55) JTD
– – PUD – – IVSEL IVCE MCUCR
Read/Write R/W RRR/W RRR/W R/W
Initial Value00000000
Bit 76543210
0x34 (0x54)
– – –JTRFWDRF BORF EXTRF PORF MCUSR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description