Datasheet

22
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
8.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clk
CPU
cycles as described in Figure 8-3.
Figure 8-3. On-chip Data SRAM Access Cycles
8.3 EEPROM Data Memory
The ATmega640/1280/1281/2560/2561 contains 4Kbytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000
write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see “Serial Downloading”
on page 338, “Programming via the JTAG Interface” on page 342, and “Programming the EEPROM” on page 333
respectively.
Figure 8-2. Data Memory Map
Address (HEX)
0 - 1F 32 Registers
20 - 5F 64 I/O Registers
60 - 1FF
416 External I/O Registers
200
Internal SRAM
(8192 × 8)
21FF
2200
External SRAM
(0 - 64K × 8)
FFFF
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction