Datasheet
Table Of Contents
- 1. Pin Configurations
- 2. Overview
- 2.1 Block Diagram
- 2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560
- 2.3 Pin Descriptions
- 2.3.1 VCC
- 2.3.2 GND
- 2.3.3 Port A (PA7..PA0)
- 2.3.4 Port B (PB7..PB0)
- 2.3.5 Port C (PC7..PC0)
- 2.3.6 Port D (PD7..PD0)
- 2.3.7 Port E (PE7..PE0)
- 2.3.8 Port F (PF7..PF0)
- 2.3.9 Port G (PG5..PG0)
- 2.3.10 Port H (PH7..PH0)
- 2.3.11 Port J (PJ7..PJ0)
- 2.3.12 Port K (PK7..PK0)
- 2.3.13 Port L (PL7..PL0)
- 2.3.14 RESET
- 2.3.15 XTAL1
- 2.3.16 XTAL2
- 2.3.17 AVCC
- 2.3.18 AREF
- 3. Resources
- 4. About Code Examples
- 5. Data Retention
- 6. Capacitive touch sensing
- 7. AVR CPU Core
- 8. AVR Memories
- 9. External Memory Interface
- 10. System Clock and Clock Options
- 10.1 Overview
- 10.2 Clock Systems and their Distribution
- 10.3 Clock Sources
- 10.4 Low Power Crystal Oscillator
- 10.5 Full Swing Crystal Oscillator
- 10.6 Low Frequency Crystal Oscillator
- 10.7 Calibrated Internal RC Oscillator
- 10.8 128kHz Internal Oscillator
- 10.9 External Clock
- 10.10 Clock Output Buffer
- 10.11 Timer/Counter Oscillator
- 10.12 System Clock Prescaler
- 10.13 Register Description
- 11. Power Management and Sleep Modes
- 12. System Control and Reset
- 13. I/O-Ports
- 13.1 Introduction
- 13.2 Ports as General Digital I/O
- 13.3 Alternate Port Functions
- 13.3.1 Alternate Functions of Port A
- 13.3.2 Alternate Functions of Port B
- 13.3.3 Alternate Functions of Port C
- 13.3.4 Alternate Functions of Port D
- 13.3.5 Alternate Functions of Port E
- 13.3.6 Alternate Functions of Port F
- 13.3.7 Alternate Functions of Port G
- 13.3.8 Alternate Functions of Port H
- 13.3.9 Alternate Functions of Port J
- 13.3.10 Alternate Functions of Port K
- 13.3.11 Alternate Functions of Port L
- 13.4 Register Description for I/O-Ports
- 13.4.1 MCUCR – MCU Control Register
- 13.4.2 PORTA – Port A Data Register
- 13.4.3 DDRA – Port A Data Direction Register
- 13.4.4 PINA – Port A Input Pins Address
- 13.4.5 PORTB – Port B Data Register
- 13.4.6 DDRB – Port B Data Direction Register
- 13.4.7 PINB – Port B Input Pins Address
- 13.4.8 PORTC – Port C Data Register
- 13.4.9 DDRC – Port C Data Direction Register
- 13.4.10 PINC– Port C Input Pins Address
- 13.4.11 PORTD – Port D Data Register
- 13.4.12 DDRD – Port D Data Direction Register
- 13.4.13 PIND – Port D Input Pins Address
- 13.4.14 PORTE – Port E Data Register
- 13.4.15 DDRE – Port E Data Direction Register
- 13.4.16 PINE – Port E Input Pins Address
- 13.4.17 PORTF – Port F Data Register
- 13.4.18 DDRF – Port F Data Direction Register
- 13.4.19 PINF – Port F Input Pins Address
- 13.4.20 PORTG – Port G Data Register
- 13.4.21 DDRG – Port G Data Direction Register
- 13.4.22 PING – Port G Input Pins Address
- 13.4.23 PORTH – Port H Data Register
- 13.4.24 DDRH – Port H Data Direction Register
- 13.4.25 PINH – Port H Input Pins Address
- 13.4.26 PORTJ – Port J Data Register
- 13.4.27 DDRJ – Port J Data Direction Register
- 13.4.28 PINJ – Port J Input Pins Address
- 13.4.29 PORTK – Port K Data Register
- 13.4.30 DDRK – Port K Data Direction Register
- 13.4.31 PINK – Port K Input Pins Address
- 13.4.32 PORTL – Port L Data Register
- 13.4.33 DDRL – Port L Data Direction Register
- 13.4.34 PINL – Port L Input Pins Address
- 14. Interrupts
- 15. External Interrupts
- 15.1 Pin Change Interrupt Timing
- 15.2 Register Description
- 15.2.1 EICRA – External Interrupt Control Register A
- 15.2.2 EICRB – External Interrupt Control Register B
- 15.2.3 EIMSK – External Interrupt Mask Register
- 15.2.4 EIFR – External Interrupt Flag Register
- 15.2.5 PCICR – Pin Change Interrupt Control Register
- 15.2.6 PCIFR – Pin Change Interrupt Flag Register
- 15.2.7 PCMSK2 – Pin Change Mask Register 2
- 15.2.8 PCMSK1 – Pin Change Mask Register 1
- 15.2.9 PCMSK0 – Pin Change Mask Register 0
- 16. 8-bit Timer/Counter0 with PWM
- 16.1 Features
- 16.2 Overview
- 16.3 Timer/Counter Clock Sources
- 16.4 Counter Unit
- 16.5 Output Compare Unit
- 16.6 Compare Match Output Unit
- 16.7 Modes of Operation
- 16.8 Timer/Counter Timing Diagrams
- 16.9 Register Description
- 16.9.1 TCCR0A – Timer/Counter Control Register A
- 16.9.2 TCCR0B – Timer/Counter Control Register B
- 16.9.3 TCNT0 – Timer/Counter Register
- 16.9.4 OCR0A – Output Compare Register A
- 16.9.5 OCR0B – Output Compare Register B
- 16.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register
- 16.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
- 17. 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5)
- 17.1 Features
- 17.2 Overview
- 17.3 Accessing 16-bit Registers
- 17.4 Timer/Counter Clock Sources
- 17.5 Counter Unit
- 17.6 Input Capture Unit
- 17.7 Output Compare Units
- 17.8 Compare Match Output Unit
- 17.9 Modes of Operation
- 17.10 Timer/Counter Timing Diagrams
- 17.11 Register Description
- 17.11.1 TCCR1A – Timer/Counter 1 Control Register A
- 17.11.2 TCCR3A – Timer/Counter 3 Control Register A
- 17.11.3 TCCR4A – Timer/Counter 4 Control Register A
- 17.11.4 TCCR5A – Timer/Counter 5 Control Register A
- 17.11.5 TCCR1B – Timer/Counter 1 Control Register B
- 17.11.6 TCCR3B – Timer/Counter 3 Control Register B
- 17.11.7 TCCR4B – Timer/Counter 4 Control Register B
- 17.11.8 TCCR5B – Timer/Counter 5 Control Register B
- 17.11.9 TCCR1C – Timer/Counter 1 Control Register C
- 17.11.10 TCCR3C – Timer/Counter 3 Control Register C
- 17.11.11 TCCR4C – Timer/Counter 4 Control Register C
- 17.11.12 TCCR5C – Timer/Counter 5 Control Register C
- 17.11.13 TCNT1H and TCNT1L – Timer/Counter 1
- 17.11.14 TCNT3H and TCNT3L – Timer/Counter 3
- 17.11.15 TCNT4H and TCNT4L –Timer/Counter 4
- 17.11.16 TCNT5H and TCNT5L –Timer/Counter 5
- 17.11.17 OCR1AH and OCR1AL – Output Compare Register 1 A
- 17.11.18 OCR1BH and OCR1BL – Output Compare Register 1 B
- 17.11.19 OCR1CH and OCR1CL – Output Compare Register 1 C
- 17.11.20 OCR3AH and OCR3AL – Output Compare Register 3 A
- 17.11.21 OCR3BH and OCR3BL – Output Compare Register 3 B
- 17.11.22 OCR3CH and OCR3CL – Output Compare Register 3 C
- 17.11.23 OCR4AH and OCR4AL – Output Compare Register 4 A
- 17.11.24 OCR4BH and OCR4BL – Output Compare Register 4 B
- 17.11.25 OCR4CH and OCR4CL –Output Compare Register 4 C
- 17.11.26 OCR5AH and OCR5AL – Output Compare Register 5 A
- 17.11.27 OCR5BH and OCR5BL – Output Compare Register 5 B
- 17.11.28 OCR5CH and OCR5CL –Output Compare Register 5 C
- 17.11.29 ICR1H and ICR1L – Input Capture Register 1
- 17.11.30 ICR3H and ICR3L – Input Capture Register 3
- 17.11.31 ICR4H and ICR4L – Input Capture Register 4
- 17.11.32 ICR5H and ICR5L – Input Capture Register 5
- 17.11.33 TIMSK1 – Timer/Counter 1 Interrupt Mask Register
- 17.11.34 TIMSK3 – Timer/Counter 3 Interrupt Mask Register
- 17.11.35 TIMSK4 – Timer/Counter 4 Interrupt Mask Register
- 17.11.36 TIMSK5 – Timer/Counter 5 Interrupt Mask Register
- 17.11.37 TIFR1 – Timer/Counter1 Interrupt Flag Register
- 17.11.38 TIFR3 – Timer/Counter3 Interrupt Flag Register
- 17.11.39 TIFR4 – Timer/Counter4 Interrupt Flag Register
- 17.11.40 TIFR5 – Timer/Counter5 Interrupt Flag Register
- 18. Timer/Counter 0, 1, 3, 4, and 5 Prescaler
- 19. Output Compare Modulator (OCM1C0A)
- 20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 20.1 Overview
- 20.2 Timer/Counter Clock Sources
- 20.3 Counter Unit
- 20.4 Modes of Operation
- 20.5 Output Compare Unit
- 20.6 Compare Match Output Unit
- 20.7 Timer/Counter Timing Diagrams
- 20.8 Asynchronous Operation of Timer/Counter2
- 20.9 Timer/Counter Prescaler
- 20.10 Register Description
- 20.10.1 TCCR2A –Timer/Counter Control Register A
- 20.10.2 TCCR2B – Timer/Counter Control Register B
- 20.10.3 TCNT2 – Timer/Counter Register
- 20.10.4 OCR2A – Output Compare Register A
- 20.10.5 OCR2B – Output Compare Register B
- 20.10.6 ASSR – Asynchronous Status Register
- 20.10.7 TIMSK2 – Timer/Counter2 Interrupt Mask Register
- 20.10.8 TIFR2 – Timer/Counter2 Interrupt Flag Register
- 20.10.9 GTCCR – General Timer/Counter Control Register
- 21. SPI – Serial Peripheral Interface
- 22. USART
- 22.1 Features
- 22.2 Overview
- 22.3 Clock Generation
- 22.4 Frame Formats
- 22.5 USART Initialization
- 22.6 Data Transmission – The USART Transmitter
- 22.7 Data Reception – The USART Receiver
- 22.8 Asynchronous Data Reception
- 22.9 Multi-processor Communication Mode
- 22.10 Register Description
- 22.11 Examples of Baud Rate Setting
- 23. USART in SPI Mode
- 24. 2-wire Serial Interface
- 25. AC – Analog Comparator
- 26. ADC – Analog to Digital Converter
- 26.1 Features
- 26.2 Operation
- 26.3 Starting a Conversion
- 26.4 Prescaling and Conversion Timing
- 26.5 Changing Channel or Reference Selection
- 26.6 ADC Noise Canceler
- 26.7 ADC Conversion Result
- 26.8 Register Description
- 26.8.1 ADMUX – ADC Multiplexer Selection Register
- 26.8.2 ADCSRB – ADC Control and Status Register B
- 26.8.3 ADCSRA – ADC Control and Status Register A
- 26.8.4 ADCL and ADCH – The ADC Data Register
- 26.8.5 ADCSRB – ADC Control and Status Register B
- 26.8.6 DIDR0 – Digital Input Disable Register 0
- 26.8.7 DIDR2 – Digital Input Disable Register 2
- 27. JTAG Interface and On-chip Debug System
- 28. IEEE 1149.1 (JTAG) Boundary-scan
- 29. Boot Loader Support – Read-While-Write Self-Programming
- 29.1 Features
- 29.2 Application and Boot Loader Flash Sections
- 29.3 Read-While-Write and No Read-While-Write Flash Sections
- 29.4 Boot Loader Lock Bits
- 29.5 Addressing the Flash During Self-Programming
- 29.6 Self-Programming the Flash
- 29.6.1 Performing Page Erase by SPM
- 29.6.2 Filling the Temporary Buffer (Page Loading)
- 29.6.3 Performing a Page Write
- 29.6.4 Using the SPM Interrupt
- 29.6.5 Consideration While Updating BLS
- 29.6.6 Prevent Reading the RWW Section During Self-Programming
- 29.6.7 Setting the Boot Loader Lock Bits by SPM
- 29.6.8 EEPROM Write Prevents Writing to SPMCSR
- 29.6.9 Reading the Fuse and Lock Bits from Software
- 29.6.10 Reading the Signature Row from Software
- 29.6.11 Preventing Flash Corruption
- 29.6.12 Programming Time for Flash when Using SPM
- 29.6.13 Simple Assembly Code Example for a Boot Loader
- 29.6.14 ATmega640 Boot Loader Parameters
- 29.6.15 ATmega1280/1281 Boot Loader Parameters
- 29.6.16 ATmega2560/2561 Boot Loader Parameters
- 29.7 Register Description
- 30. Memory Programming
- 30.1 Program And Data Memory Lock Bits
- 30.2 Fuse Bits
- 30.3 Signature Bytes
- 30.4 Calibration Byte
- 30.5 Page Size
- 30.6 Parallel Programming Parameters, Pin Mapping, and Commands
- 30.7 Parallel Programming
- 30.7.1 Enter Programming Mode
- 30.7.2 Considerations for Efficient Programming
- 30.7.3 Chip Erase
- 30.7.4 Programming the Flash
- 30.7.5 Programming the EEPROM
- 30.7.6 Reading the Flash
- 30.7.7 Reading the EEPROM
- 30.7.8 Programming the Fuse Low Bits
- 30.7.9 Programming the Fuse High Bits
- 30.7.10 Programming the Extended Fuse Bits
- 30.7.11 Programming the Lock Bits
- 30.7.12 Reading the Fuse and Lock Bits
- 30.7.13 Reading the Signature Bytes
- 30.7.14 Reading the Calibration Byte
- 30.7.15 Parallel Programming Characteristics
- 30.8 Serial Downloading
- 30.9 Programming via the JTAG Interface
- 30.9.1 Programming Specific JTAG Instructions
- 30.9.2 AVR_RESET (0xC)
- 30.9.3 PROG_ENABLE (0x4)
- 30.9.4 PROG_COMMANDS (0x5)
- 30.9.5 PROG_PAGELOAD (0x6)
- 30.9.6 PROG_PAGEREAD (0x7)
- 30.9.7 Data Registers
- 30.9.8 Reset Register
- 30.9.9 Programming Enable Register
- 30.9.10 Programming Command Register
- 30.9.11 Flash Data Byte Register
- 30.9.12 Programming Algorithm
- 30.9.13 Entering Programming Mode
- 30.9.14 Leaving Programming Mode
- 30.9.15 Performing Chip Erase
- 30.9.16 Programming the Flash
- 30.9.17 Reading the Flash
- 30.9.18 Programming the EEPROM
- 30.9.19 Reading the EEPROM
- 30.9.20 Programming the Fuses
- 30.9.21 Programming the Lock Bits
- 30.9.22 Reading the Fuses and Lock Bits
- 30.9.23 Reading the Signature Bytes
- 30.9.24 Reading the Calibration Byte
- 31. Electrical Characteristics
- 32. Typical Characteristics
- 32.1 Active Supply Current
- 32.2 Idle Supply Current
- 32.3 Power-down Supply Current
- 32.4 Power-save Supply Current
- 32.5 Standby Supply Current
- 32.6 Pin Pull-up
- 32.7 Pin Driver Strength
- 32.8 Pin Threshold and Hysteresis
- 32.9 BOD Threshold and Analog Comparator Offset
- 32.10 Internal Oscillator Speed
- 32.11 Current Consumption of Peripheral Units
- 32.12 Current Consumption in Reset and Reset Pulsewidth
- 33. Register Summary
- 34. Instruction Set Summary
- 35. Ordering Information
- 36. Packaging Information
- 37. Errata
- 37.1 ATmega640 rev. B
- 37.2 ATmega640 rev. A
- 37.3 ATmega1280 rev. B
- 37.4 ATmega1280 rev. A
- 37.5 ATmega1281 rev. B
- 37.6 ATmega1281 rev. A
- 37.7 ATmega2560 rev. F
- 37.8 ATmega2560 rev. E
- 37.9 ATmega2560 rev. D
- 37.10 ATmega2560 rev. C
- 37.11 ATmega2560 rev. B
- 37.12 ATmega2560 rev. A
- 37.13 ATmega2561 rev. F
- 37.14 ATmega2561 rev. E
- 37.15 ATmega2561 rev. D
- 37.16 ATmega2561 rev. C
- 37.17 ATmega2561 rev. B
- 37.18 ATmega2561 rev. A
- 38. Datasheet Revision History
- 38.1 Rev. 2549Q-02/2014
- 38.2 Rev. 2549P-10/2012
- 38.3 Rev. 2549O-05/2012
- 38.4 Rev. 2549N-05/2011
- 38.5 Rev. 2549M-09/2010
- 38.6 Rev. 2549L-08/07
- 38.7 Rev. 2549K-01/07
- 38.8 Rev. 2549J-09/06
- 38.9 Rev. 2549I-07/06
- 38.10 Rev. 2549H-06/06
- 38.11 Rev. 2549G-06/06
- 38.12 Rev. 2549F-04/06
- 38.13 Rev. 2549E-04/06
- 38.14 Rev. 2549D-12/05
- 38.15 Rev. 2549C-09/05
- 38.16 Rev. 2549B-05/05
- 38.17 Rev. 2549A-03/05
145
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functional-
ity and location of these bits are compatible with previous versions of the timer.
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 152.
17.9.1 Normal Mode
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum
16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Coun-
ter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in
this case behaves like a 17
th
bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by software. There are no
special cases to consider in the Normal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the
external events must not exceed the resolution of the counter. If the interval between events are too long, the timer
overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
17.9.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register are used to manipu-
late the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches
either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the
Table 17-2. Waveform Generation Mode Bit Description
(1)
Mode WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter
Mode of Operation TOP
Update of
OCRnx at
TOVn Flag
Set on
00 0 0 0 Normal 0xFFFF Immediate MAX
10 0 0 1PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
20 0 1 0PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
30 0 1 1PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCRnA Immediate MAX
50 1 0 1 Fast PWM, 8-bit 0x00FF BOTTOM TOP
60 1 1 0 Fast PWM, 9-bit 0x01FF BOTTOM TOP
70 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP
81 0 0 0
PWM, Phase and Frequency
Correct
ICRn BOTTOM BOTTOM
91 0 0 1
PWM,Phase and Frequency
Correct
OCRnA BOTTOM BOTTOM
101010PWM, Phase Correct ICRn TOP BOTTOM
111011PWM, Phase Correct OCRnA TOP BOTTOM
12 1 1 0 0 CTC ICRn Immediate MAX
131101 (Reserved) – – –
141110 Fast PWMICRnBOTTOMTOP
151111 Fast PWM OCRnA BOTTOM TOP