Datasheet

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Table Of Contents

1. Pin Configurations
2. Overview
- 2.1 Block Diagram
- 2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560
- 2.3 Pin Descriptions
3. Resources
4. About Code Examples
5. Data Retention
6. Capacitive touch sensing
7. AVR CPU Core
- 7.1 Introduction
- 7.2 Architectural Overview
- 7.3 ALU – Arithmetic Logic Unit
- 7.4 Status Register
  - 7.4.1 SREG – AVR Status Register
- 7.5 General Purpose Register File
  - 7.5.1 The X-register, Y-register, and Z-register
- 7.6 Stack Pointer
  - 7.6.1 RAMPZ – Extended Z-pointer Register for ELPM/SPM
  - 7.6.2 EIND – Extended Indirect Register
- 7.7 Instruction Execution Timing
- 7.8 Reset and Interrupt Handling
  - 7.8.1 Interrupt Response Time
8. AVR Memories
- 8.1 In-System Reprogrammable Flash Program Memory
- 8.2 SRAM Data Memory
  - 8.2.1 Data Memory Access Times
- 8.3 EEPROM Data Memory
  - 8.3.1 EEPROM Read/Write Access
  - 8.3.2 Preventing EEPROM Corruption
- 8.4 I/O Memory
  - 8.4.1 General Purpose I/O Registers
9. External Memory Interface
- 9.1 Overview
- 9.2 Register Description
  - 9.2.1 EEPROM registers
- 9.3 General Purpose registers
- 9.4 External Memory registers
  - 9.4.1 XMCRA – External Memory Control Register A
  - 9.4.2 XMCRB – External Memory Control Register B
10. System Clock and Clock Options
- 10.1 Overview
- 10.2 Clock Systems and their Distribution
- 10.3 Clock Sources
  - 10.3.1 Default Clock Source
  - 10.3.2 Clock Start-up Sequence
- 10.4 Low Power Crystal Oscillator
- 10.5 Full Swing Crystal Oscillator
- 10.6 Low Frequency Crystal Oscillator
- 10.7 Calibrated Internal RC Oscillator
- 10.8 128kHz Internal Oscillator
- 10.9 External Clock
- 10.10 Clock Output Buffer
- 10.11 Timer/Counter Oscillator
- 10.12 System Clock Prescaler
- 10.13 Register Description
  - 10.13.1 OSCCAL – Oscillator Calibration Register
  - 10.13.2 CLKPR – Clock Prescale Register
11. Power Management and Sleep Modes
- 11.1 Sleep Modes
- 11.2 Idle Mode
- 11.3 ADC Noise Reduction Mode
- 11.4 Power-down Mode
- 11.5 Power-save Mode
- 11.6 Standby Mode
- 11.7 Extended Standby Mode
- 11.8 Power Reduction Register
- 11.9 Minimizing Power Consumption
- 11.10 Register Description
12. System Control and Reset
- 12.1 Resetting the AVR
- 12.2 Reset Sources
- 12.3 Internal Voltage Reference
  - 12.3.1 Voltage Reference Enable Signals and Start-up Time
- 12.4 Watchdog Timer
  - 12.4.1 Features
  - 12.4.2 Overview
- 12.5 Register Description
  - 12.5.1 MCUSR – MCU Status Register
  - 12.5.2 WDTCSR – Watchdog Timer Control Register
13. I/O-Ports
- 13.1 Introduction
- 13.2 Ports as General Digital I/O
- 13.3 Alternate Port Functions
- 13.4 Register Description for I/O-Ports
14. Interrupts
- 14.1 Interrupt Vectors in ATmega640/1280/1281/2560/2561
- 14.2 Reset and Interrupt Vector placement
- 14.3 Moving Interrupts Between Application and Boot Section
- 14.4 Register Description
  - 14.4.1 MCUCR – MCU Control Register
15. External Interrupts
- 15.1 Pin Change Interrupt Timing
- 15.2 Register Description
16. 8-bit Timer/Counter0 with PWM
- 16.1 Features
- 16.2 Overview
  - 16.2.1 Registers
  - 16.2.2 Definitions
- 16.3 Timer/Counter Clock Sources
- 16.4 Counter Unit
- 16.5 Output Compare Unit
- 16.6 Compare Match Output Unit
  - 16.6.1 Compare Output Mode and Waveform Generation
- 16.7 Modes of Operation
- 16.8 Timer/Counter Timing Diagrams
- 16.9 Register Description
17. 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5)
- 17.1 Features
- 17.2 Overview
  - 17.2.1 Registers
  - 17.2.2 Definitions
- 17.3 Accessing 16-bit Registers
  - 17.3.1 Reusing the Temporary High Byte Register
- 17.4 Timer/Counter Clock Sources
- 17.5 Counter Unit
- 17.6 Input Capture Unit
- 17.7 Output Compare Units
- 17.8 Compare Match Output Unit
  - 17.8.1 Compare Output Mode and Waveform Generation
- 17.9 Modes of Operation
- 17.10 Timer/Counter Timing Diagrams
- 17.11 Register Description
18. Timer/Counter 0, 1, 3, 4, and 5 Prescaler
- 18.1 Internal Clock Source
- 18.2 Prescaler Reset
- 18.3 External Clock Source
- 18.4 Register Description
  - 18.4.1 GTCCR – General Timer/Counter Control Register
19. Output Compare Modulator (OCM1C0A)
- 19.1 Overview
- 19.2 Description
  - 19.2.1 Timing example
20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 20.1 Overview
  - 20.1.1 Registers
  - 20.1.2 Definitions
- 20.2 Timer/Counter Clock Sources
- 20.3 Counter Unit
- 20.4 Modes of Operation
- 20.5 Output Compare Unit
- 20.6 Compare Match Output Unit
  - 20.6.1 Compare Output Mode and Waveform Generation
- 20.7 Timer/Counter Timing Diagrams
- 20.8 Asynchronous Operation of Timer/Counter2
- 20.9 Timer/Counter Prescaler
- 20.10 Register Description
21. SPI – Serial Peripheral Interface
- 21.1 SS Pin Functionality
- 21.2 Register Description
22. USART
- 22.1 Features
- 22.2 Overview
- 22.3 Clock Generation
- 22.4 Frame Formats
  - 22.4.1 Parity Bit Calculation
- 22.5 USART Initialization
- 22.6 Data Transmission – The USART Transmitter
- 22.7 Data Reception – The USART Receiver
- 22.8 Asynchronous Data Reception
- 22.9 Multi-processor Communication Mode
  - 22.9.1 Using MPCMn
- 22.10 Register Description
- 22.11 Examples of Baud Rate Setting
23. USART in SPI Mode
- 23.1 Overview
- 23.2 USART MSPIM vs. SPI
  - 23.2.1 Clock Generation
- 23.3 SPI Data Modes and Timing
- 23.4 Frame Formats
  - 23.4.1 USART MSPIM Initialization
- 23.5 Data Transfer
  - 23.5.1 Transmitter and Receiver Flags and Interrupts
  - 23.5.2 Disabling the Transmitter or Receiver
- 23.6 USART MSPIM Register Description
24. 2-wire Serial Interface
- 24.1 Features
- 24.2 2-wire Serial Interface Bus Definition
  - 24.2.1 TWI Terminology
  - 24.2.2 Electrical Interconnection
- 24.3 Data Transfer and Frame Format
- 24.4 Multi-master Bus Systems, Arbitration, and Synchronization
- 24.5 Overview of the TWI Module
- 24.6 Using the TWI
- 24.7 Transmission Modes
- 24.8 Multi-master Systems and Arbitration
- 24.9 Register Description
25. AC – Analog Comparator
- 25.1 Analog Comparator Multiplexed Input
- 25.2 Register Description
26. ADC – Analog to Digital Converter
- 26.1 Features
- 26.2 Operation
- 26.3 Starting a Conversion
- 26.4 Prescaling and Conversion Timing
  - 26.4.1 Differential Channels
- 26.5 Changing Channel or Reference Selection
  - 26.5.1 ADC Input Channels
  - 26.5.2 ADC Voltage Reference
- 26.6 ADC Noise Canceler
- 26.7 ADC Conversion Result
- 26.8 Register Description
27. JTAG Interface and On-chip Debug System
- 27.1 Features
- 27.2 Overview
- 27.3 TAP - Test Access Port
  - 27.3.1 TAP Controller
- 27.4 Using the Boundary-scan Chain
- 27.5 Using the On-chip Debug System
- 27.6 On-chip Debug Specific JTAG Instructions
- 27.7 Using the JTAG Programming Capabilities
- 27.8 Bibliography
- 27.9 On-chip Debug Related Register in I/O Memory
  - 27.9.1 OCDR – On-chip Debug Register
28. IEEE 1149.1 (JTAG) Boundary-scan
- 28.1 Features
- 28.2 System Overview
- 28.3 Data Registers
- 28.4 Boundary-scan Specific JTAG Instructions
- 28.5 Boundary-scan Chain
  - 28.5.1 Scanning the Digital Port Pins
  - 28.5.2 Scanning the RESET Pin
- 28.6 Boundary-scan Related Register in I/O Memory
  - 28.6.1 MCUCR – MCU Control Register
  - 28.6.2 MCUSR – MCU Status Register
- 28.7 ATmega640/1280/1281/2560/2561 Boundary-scan Order
- 28.8 Boundary-scan Description Language Files
29. Boot Loader Support – Read-While-Write Self-Programming
- 29.1 Features
- 29.2 Application and Boot Loader Flash Sections
  - 29.2.1 Application Section
  - 29.2.2 BLS – Boot Loader Section
- 29.3 Read-While-Write and No Read-While-Write Flash Sections
  - 29.3.1 RWW – Read-While-Write Section
  - 29.3.2 NRWW – No Read-While-Write Section
- 29.4 Boot Loader Lock Bits
  - 29.4.1 Entering the Boot Loader Program
- 29.5 Addressing the Flash During Self-Programming
- 29.6 Self-Programming the Flash
- 29.7 Register Description
  - 29.7.1 SPMCSR – Store Program Memory Control and Status Register
30. Memory Programming
- 30.1 Program And Data Memory Lock Bits
- 30.2 Fuse Bits
  - 30.2.1 Latching of Fuses
- 30.3 Signature Bytes
- 30.4 Calibration Byte
- 30.5 Page Size
- 30.6 Parallel Programming Parameters, Pin Mapping, and Commands
  - 30.6.1 Signal Names
- 30.7 Parallel Programming
- 30.8 Serial Downloading
- 30.9 Programming via the JTAG Interface
31. Electrical Characteristics
- 31.1 DC Characteristics
- 31.2 Speed Grades
  - 31.2.1 8MHz
  - 31.2.2 16MHz
- 31.3 Clock Characteristics
  - 31.3.1 Calibrated Internal RC Oscillator Accuracy
  - 31.3.2 External Clock Drive Waveforms
- 31.4 External Clock Drive
- 31.5 System and Reset Characteristics
  - 31.5.1 Standard Power-On Reset
  - 31.5.2 Enhanced Power-On Reset
- 31.6 2-wire Serial Interface Characteristics
- 31.7 SPI Timing Characteristics
- 31.8 ADC Characteristics – Preliminary Data
- 31.9 External Data Memory Timing
32. Typical Characteristics
- 32.1 Active Supply Current
- 32.2 Idle Supply Current
  - 32.2.1 Supply Current of IO modules
- 32.3 Power-down Supply Current
- 32.4 Power-save Supply Current
- 32.5 Standby Supply Current
- 32.6 Pin Pull-up
- 32.7 Pin Driver Strength
- 32.8 Pin Threshold and Hysteresis
- 32.9 BOD Threshold and Analog Comparator Offset
- 32.10 Internal Oscillator Speed
- 32.11 Current Consumption of Peripheral Units
- 32.12 Current Consumption in Reset and Reset Pulsewidth
33. Register Summary
34. Instruction Set Summary
35. Ordering Information
- 35.1 ATmega640
- 35.2 ATmega1280
- 35.3 ATmega1281
- 35.4 ATmega2560
- 35.5 ATmega2561
36. Packaging Information
- 36.1 100A
- 36.2 100C1
- 36.3 64A
- 36.4 64M2
37. Errata
- 37.1 ATmega640 rev. B
- 37.2 ATmega640 rev. A
- 37.3 ATmega1280 rev. B
- 37.4 ATmega1280 rev. A
- 37.5 ATmega1281 rev. B
- 37.6 ATmega1281 rev. A
- 37.7 ATmega2560 rev. F
- 37.8 ATmega2560 rev. E
- 37.9 ATmega2560 rev. D
- 37.10 ATmega2560 rev. C
- 37.11 ATmega2560 rev. B
- 37.12 ATmega2560 rev. A
- 37.13 ATmega2561 rev. F
- 37.14 ATmega2561 rev. E
- 37.15 ATmega2561 rev. D
- 37.16 ATmega2561 rev. C
- 37.17 ATmega2561 rev. B
- 37.18 ATmega2561 rev. A
38. Datasheet Revision History
- 38.1 Rev. 2549Q-02/2014
- 38.2 Rev. 2549P-10/2012
- 38.3 Rev. 2549O-05/2012
- 38.4 Rev. 2549N-05/2011
- 38.5 Rev. 2549M-09/2010
- 38.6 Rev. 2549L-08/07
- 38.7 Rev. 2549K-01/07
- 38.8 Rev. 2549J-09/06
- 38.9 Rev. 2549I-07/06
- 38.10 Rev. 2549H-06/06
- 38.11 Rev. 2549G-06/06
- 38.12 Rev. 2549F-04/06
- 38.13 Rev. 2549E-04/06
- 38.14 Rev. 2549D-12/05
- 38.15 Rev. 2549C-09/05
- 38.16 Rev. 2549B-05/05
- 38.17 Rev. 2549A-03/05

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

2549Q–AVR–02/2014

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that is, counter reso-

lution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the

Waveform Generator.

Figure 17-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indi-

cates the device number (n = n

for Timer/Counter n), and the “x” indicates Output Compare unit (A/B/C). The

elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded.

Figure 17-4. Output Compare Unit, Block Diagram

The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For

the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double

buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting

sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby

making the output glitch-free.

The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the

CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx

directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the

Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is

not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as

when accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Register since the

compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first. When the high byte I/O

location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte

(OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCRnx

buffer or OCRnx Compare Register in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 135.

OCFnx (Int.Req.)

= (16-bit Comparator )

OCRnx Buffer (16-bit Register)

OCRnxH Buf. (8-bit)

OCnx

TEMP (8-bit)

DATA BU S (8-bit)

OCRnxL Buf. (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

COMnx1:0WGMn3:0

OCRnx (16-bit Register)

OCRnxH (8-bit) OCRnxL (8-bit)

Waveform Generator

TOP

BOTTOM