Datasheet

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is
referred to as the timer clock (clk
T
n
).
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all
time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency
output on the Output Compare pin (OCnA/B/C). See “Output Compare Units” on page 141. The compare match
event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare inter-
rupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on
either the Input Capture pin (ICPn) or on the Analog Comparator pins (see “AC – Analog Comparator” on page
265). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing
noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the
OCRnA Register, the ICRn Register, or by a set of fixed values. When using OCRnA as TOP value in a PWM
mode, the OCRnA Register can not be used for generating a PWM output. However, the TOP value will in this
case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the
ICRn Register can be used as an alternative, freeing the OCRnA to be used as PWM output.
17.2.2 Definitions
The following definitions are used extensively throughout the document:
17.3 Accessing 16-bit Registers
The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data
bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-
bit register for temporary storing of the high byte of the 16-bit access. The same Temporary Register is shared
between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write opera-
tion. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the Temporary Register,
and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-
bit register is read by the CPU, the high byte of the 16-bit register is copied into the Temporary Register in the
same clock cycle as the low byte is read.
Not all 16-bit accesses uses the Temporary Register for the high byte. Reading the OCRnA/B/C 16-bit registers
does not involve using the Temporary Register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read
before the high byte.
The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates
the temporary register. The same principle can be used directly for accessing the OCRnA/B/C and ICRn Registers.
Note that when using “C”, the compiler handles the 16-bit access.
Table 17-1. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or
0x03FF, or to the value stored in the OCRnA or ICRn Register. The assignment is dependent of
the mode of operation.