Atmel ATmega640/V-1280/V-1281/V-2560/V-2561/V 8-bit Atmel Microcontroller with 16/32/64KB In-System Programmable Flash DATASHEET Features • • • High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller Advanced RISC Architecture – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments – 64K/128K/256KBytes of In-System
1. Pin Configurations 81 80 PA1 (AD1) 82 PA2 (AD2) 83 PJ7 84 PA0 (AD0) 85 GND 86 VCC 87 PK7 (ADC15/PCINT23) 88 PK5 (ADC13/PCINT21) 89 PK6 (ADC14/PCINT22) 90 PK3 (ADC11/PCINT19) 91 PK4 (ADC12/PCINT20) 92 PK1 (ADC9/PCINT17) 93 PK2 (ADC10/PCINT18) PK0 (ADC8/PCINT16) 94 PF7 (ADC7/TDI) 95 PF6 (ADC6/TDO) 96 PF4 (ADC4/TCK) 97 PF5 (ADC5/TMS) PF1 (ADC1) 98 PF2 (ADC2) PF0 (ADC0) 100 99 PF3 (ADC3) GND AREF TQFP-pinout ATmega640/1280/2560 AVCC Figure 1-1.
Figure 1-2. CBGA-pinout ATmega640/1280/2560 Top view 1 2 3 4 5 6 7 Bottom view 8 9 10 10 9 8 7 6 5 4 3 2 1 A A B B C C D D E E F F G G H H J J K K Table 1-1.
(OC0B) PG5 1 (RXD0/PCINT8/PDI) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ATmega1281/2561 64 Figure 1-3.
2. Overview The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PF7..0 PK7..0 PORT F (8) PORT K (8) PJ7..0 PE7..
The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4Kbytes EEPROM, 8Kbytes SRAM, 54/86 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), six flexible Timer/Counters with compare modes and PWM, four USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with
2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560 Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2-1 summarizes the different configurations for the six devices. Table 2-1. 2.3 2.3.
2.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
2.3.12 Port K (PK7..PK0) Port K serves as analog inputs to the A/D Converter. Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port K output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset condition becomes active, even if the clock is not running.
3. Resources A comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details.
7. AVR CPU Core 7.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 7-1.
ands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
7.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
• Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU General Purpose Working Registers 7 0 Addr.
7.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.
7.6.1 RAMPZ – Extended Z-pointer Register for ELPM/SPM Bit 7 6 5 4 3 2 1 0 0x3B (0x5B) RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4. Note that LPM is not affected by the RAMPZ setting. Figure 7-4.
Figure 7-6. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-7.
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags.
7.8.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
8. AVR Memories This section describes the different memories in the ATmega640/1280/1281/2560/2561. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega640/1280/1281/2560/2561 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.
When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories are accessed, the read and write strobe pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the XMCRA Register.
Figure 8-2. Data Memory Map Address (HEX) 0 - 1F 32 Registers 20 - 5F 64 I/O Registers 60 - 1FF 416 External I/O Registers 200 Internal SRAM (8192 × 8) 21FF 2200 External SRAM (0 - 64K × 8) FFFF 8.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 8-3. Figure 8-3.
8.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space, see “Register Description” on page 34. The write access time for the EEPROM is given in Table 8-1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down.
Assembly Code Example(1) EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example(1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
8.4 I/O Memory The I/O space definition of the ATmega640/1280/1281/2560/2561 is shown in “Register Summary” on page 399. All ATmega640/1280/1281/2560/2561 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
9. External Memory Interface With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCD-display, A/D, and D/A. The main features are: • • • • 9.
The control bits for the External Memory Interface are located in two registers, the External Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB. When the XMEM interface is enabled, the XMEM interface will override the setting in the data direction registers that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alternate functions in section “I/O-Ports” on page 67.
9.1.3 Pull-up and Bus-keeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep. The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be disabled and enabled in software as described in “XMCRB – External Memory Control Register B” on page 38.
Figure 9-4. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev. data Address Data Write XX WR Address Read Data Data RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
Figure 9-6. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1) T1 T2 T3 T4 T5 T6 T7 System Clock (CLKCPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev. data XX Write Address Data WR Address Read Data Data RD Note: 9.1.5 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
9.1.6 Using all 64Kbytes Locations of External Memory Since the External Memory is mapped after the Internal Memory as shown in Figure 9-1 on page 27, only 56Kbytes of External Memory is available by default (address space 0x0000 to 0x21FF is reserved for internal memory). However, it is possible to take advantage of the entire External Memory by masking the higher address bits to zero. This can be done by using the XMMn bits and control by software the most significant bits of the address.
Assembly Code Example(1) ; ; ; ; ; OFFSET is defined to 0x4000 to ensure external memory access Configure Port C (address high byte) to output 0x00 when the pins are released for normal Port Pin operation ldi r16, 0xFF out DDRC, r16 ldi r16, 0x00 out PORTC, r16 ; release PC7:6 ldi r16, (1<
9.2 9.2.1 Register Description EEPROM registers 9.2.1.
Table 9-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time Operation 0 0 3.4ms Erase and Write in one operation (Atomic Operation) 0 1 1.8ms Erase only 1 0 1.8ms Write only 1 1 – Reserved for future use • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.
The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. 9.3 9.3.1 General Purpose registers GPIOR2 – General Purpose I/O Register 2 Bit 9.3.2 9.4.
Table 9-2.
9.4.2 XMCRB – External Memory Control Register B Bit 7 6 5 4 3 2 1 0 XMBK – – – – XMM2 XMM1 XMM0 Read/Write R/W R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x75) XMCRB • Bit 7– XMBK: External Memory Bus-keeper Enable Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-stated the lines. Writing XMBK to zero disables the bus keeper.
10. System Clock and Clock Options This section describes the clock options for the AVR microcontroller. 10.1 Overview Figure 10-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 50. The clock systems are detailed below. Figure 10-1.
10.2.3 Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 10.2.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a realtime counter even when the device is in sleep mode. 10.2.
Table 10-2. Number of Watchdog Oscillator Cycles Typical Time-out (VCC = 5.0V) Typical Time-out (VCC = 3.0V) Number of Cycles 0ms 0ms 0 4.1ms 4.3ms 512 65ms 69ms 8K (8,192) Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The delay will not monitor the actual voltage and it will be required to select a delay longer than the VCC rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used.
Table 10-3. Low Power Crystal Oscillator Operating Modes(3) Frequency Range [MHz] CKSEL3:1(1) 0.4 - 0.9 100 – 0.9 - 3.0 101 12 - 22 3.0 - 8.0 110 12 - 22 111 12 - 22 (4) 8.0 - 16.0 Notes: Recommended Range for Capacitors C1 and C2 [pF] (2) 1. This is the recommended CKSEL settings for the different frequency ranges. 2. This option should not be used with crystals, only with ceramic resonators. 3.
Table 10-5. Frequency Range [MHz] CKSEL3:1 Recommended Range for Capacitors C1 and C2 [pF] 0.4 - 16 011 12 - 22 Note: 1. If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device. Table 10-6.
The capacitance (Ce + Ci) needed at each XTAL/TOSC pin can be calculated by using: Ce + Ci = 2 * CL - Cs where: Ce - is optional external capacitors as described in Figure 10-3. Ci - is the pin capacitance in Table 10-7 on page 43. CL - is the load capacitance for a 32.768kHz crystal specified by the crystal vendor. CS - is the total stray capacitance for one XTAL/TOSC pin.
10.7 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 31-1 on page 359 and “Internal Oscillator Speed” on page 392 for more details. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 47 for more details.
Table 10-12. Start-up Times for the 128kHz Internal Oscillator Power Conditions Start-up Time from Power-down and Power-save Additional Delay from Reset SUT1:0 BOD enabled 6CK 14CK 00 Fast rising power 6CK 14CK + 4ms 01 Slowly rising power 6CK 14CK + 64ms 10 Reserved 10.9 11 External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 10-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 10-4.
10.10 Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO.
10.13 Register Description 10.13.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
Table 10-15.
11. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 11.1 Sleep Modes Figure 10-1 on page 39 presents the different clock systems in the ATmega640/1280/1281/2560/2561, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
11.3 ADC Noise Reduction Mode When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, 2-wire Serial Interface address match, Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements.
11.8 Power Reduction Register The Power Reduction Register (PRR), see “PRR0 – Power Reduction Register 0” on page 55 and “PRR1 – Power Reduction Register 1” on page 56, provides a method for stopping the clock to individual peripherals to reduce power consumption. Note that when the clock for a peripheral is stopped, then: • The current state of the peripheral is frozen • The associated registers can not be read or written • Resources used by the peripherals (for example I/O pin, etc.
11.9.5 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Interrupts” on page 101 for details on how to configure the Watchdog Timer. 11.9.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.
11.10 Register Description 11.10.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 11-2. Table 11-2.
11.10.2 PRR0 – Power Reduction Register 0 Bit 7 6 5 4 3 2 1 0 PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x64) PRR0 • Bit 7 - PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.
11.10.3 PRR1 – Power Reduction Register 1 Bit 7 6 5 4 3 2 1 0 (0x65) – – PRTIM5 PRTIM4 PRTIM3 PRUSART3 PRUSART2 PRUSART1 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRR1 • Bit 7:6 - Res: Reserved bits These bits are reserved and will always read as zero. • Bit 5 - PRTIM5: Power Reduction Timer/Counter5 Writing a logic one to this bit shuts down the Timer/Counter5 module.
12. System Control and Reset 12.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 12-1. Reset Logic DATA BUS AVCC PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Brown-out Reset Circuit BODLEVEL [2..0] Power-on Reset Circuit Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 12.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characteristics” on page 360.
Figure 12-3. MCU Start-up, RESET Extended Externally VCC VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET 12.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 360) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Figure 12-5. Brown-out Reset During Operation AVCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 12.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. See “Watchdog Timer” on page 53. for details on operation of the Watchdog Timer. Figure 12-6. Watchdog Reset During Operation CC CK 12.
12.4 12.4.1 Watchdog Timer Features • Clocked from separate On-chip Oscillator • Three Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 128kHz OSCILLATOR WATCHDOG RESET WDE OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K Figure 12-7. Watchdog Timer WDP0 WDP1 WDP2 WDP3 MCU RESET WDIF WDIE 12.4.
Assembly Code Example(1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<
Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence in r16, WDTCSR ori r16, (1<
12.5 12.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – – – JTRF WDRF BORF EXTRF PORF Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 MCUSR See Bit Description • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
12.5.2 WDTCSR – Watchdog Timer Control Register Bit 7 6 5 4 3 2 1 0 WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 (0x60) WDTCSR • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
Table 12-2. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16ms 0 0 0 1 4K (4096) cycles 32ms 0 0 1 0 8K (8192) cycles 64ms 0 0 1 1 16K (16384) cycles 0.125s 0 1 0 0 32K (32768) cycles 0.25s 0 1 0 1 64K (65536) cycles 0.5s 0 1 1 0 128K (131072) cycles 1.0s 0 1 1 1 256K (262144) cycles 2.0s 1 0 0 0 512K (524288) cycles 4.
13. I/O-Ports 13.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
13.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 13-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx SLEEP WPx RRx SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 13.2.
13.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up.
LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 13-4.
Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
13.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
Figure 13-5.
Table 13-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 13-5 on page 73 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 13-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
13.3.1 Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 13-3.
Table 13-5. 13.3.
• OC1B/PCINT6, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT6, Pin Change Interrupt source 6: The PB6 pin can serve as an external interrupt source.
Table 13-7 and Table 13-8 relate the alternate functions of Port B to the overriding signals shown in Figure 13-5 on page 73. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source. Table 13-7.
13.3.3 Alternate Functions of Port C The Port C alternate function is as follows: Table 13-9.
Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0 13.3.
• INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. • INT2/RXD1 – Port D, Bit 2 INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU. RXD1, Receive Data (Data input pin for the USART1).
Table 13-14.
• INT7/ICP3/CLKO – Port E, Bit 7 INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. ICP3, Input Capture Pin 3: The PE7 pin can act as an input capture pin for Timer/Counter3. CLKO - Divided System Clock: The divided system clock can be output on the PE7 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTE7 and DDE7 settings. It will also be output during reset.
• PDI/RXD0/PCINT8 – Port E, Bit 0 PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega1281/2561. For ATmega640/1280/2560 this function is placed on MOSI. RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.
13.3.6 Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 13-18. If some Port F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. Table 13-18.
Table 13-19. Overriding Signals for Alternate Functions in PF7:PF4 Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV 1 0 1 1 DDOE JTAGEN JTAGEN JTAGEN JTAGEN DDOV 0 SHIFT_IR + SHIFT_DR 0 0 PVOE 0 JTAGEN 0 0 PVOV 0 TDO 0 0 DIEOE JTAGEN JTAGEN JTAGEN JTAGEN DIEOV 0 0 0 0 DI – – – – AIO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5 INPUT TCK/ADC4 INPUT Table 13-20.
• OC0B – Port G, Bit 5 OC0B, Output Compare match B output: The PG5 pin can serve as an external output for the TImer/Counter0 Output Compare. The pin has to be configured as an output (DDG5 set) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.
Table 13-23. Overriding Signals for Alternate Functions in PG3:PG0 13.3.8 Signal Name PG3/TOSC2 PG2/ALE/A7 PG1/RD PG0/WR PUOE AS2 • EXCLK SRE SRE SRE PUOV 0 0 0 0 DDOE AS2 • EXCLK SRE SRE SRE DDOV 0 1 1 1 PVOE 0 SRE SRE SRE PVOV 0 ALE RD WR PTOE – – – – DIEOE AS2 • EXCLK 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO T/C2 OSC OUTPUT – – – Alternate Functions of Port H The Port H alternate pin configuration is as follows: Table 13-24.
• OC4B – Port H, Bit 4 OC4B, Output Compare Match B output: The PH4 pin can serve as an external output for the Timer/Counter2 Output Compare B. The pin has to be configured as an output (DDH4 set) to serve this function. The OC4B pin is also the output pin for the PWM mode timer function. • OC4A – Port H, Bit 3 OC4C, Output Compare Match A output: The PH3 pin can serve as an external output for the Timer/Counter4 Output Compare A. The pin has to be configured as an output (DDH3 set) to serve this function.
Table 13-26. Overriding Signals for Alternate Functions in PH3:PH0 13.3.
• RXD3/PCINT9 - Port J, Bit 0 RXD3, USART3 Receive pin. Receive Data (Data input pin for the USART3). When the USART3 Receiver is enabled, this pin is configured as an input regardless of the value of DDJ0. When the USART3 forces this pin to be an input, a logical one in PORTJ0 will turn on the internal pull-up. PCINT9, Pin Change Interrupt Source 9. The PJ0 pin can serve as External Interrupt Sources.
Table 13-28. Overriding Signals for Alternate Functions in PJ7:PJ4 Signal Name PJ7 PJ6/ PCINT15 PJ5/ PCINT14 PJ4/ PCINT13 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE - - - - DIEOE 0 PCINT15·PCIE1 PCINT14·PCIE1 PCINT13·PCIE1 DIEOV 0 1 1 1 DI 0 PCINT15 INPUT PCINT14 INPUT PCINT13 INPUT AIO - - - - Table 13-29. Overriding Signals for Alternate Functions in PJ3:PJ0 13.3.
Table 13-30.
13.3.11 Alternate Functions of Port L The Port L alternate pin configuration is as follows: Table 13-33.
Table 13-34 and Table 13-35 relates the alternate functions of Port L to the overriding signals shown in Figure 135 on page 73. Table 13-34. Overriding Signals for Alternate Functions in PL7:PL4 Signal Name PL7 PL6 PL5/OC5C PL4/OC5B PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE – – 0 0 DDOV – – 0 0 PVOE – – OC5C ENABLE OC5B ENABLE PVOV – – OC5C OC5B PTOE – – – – DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI 0 0 0 0 AIO – – – – Table 13-35.
13.4 13.4.1 Register Description for I/O-Ports MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the I/O ports pull-up resistors are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-up resistor ({DDxn, PORTxn} = 0b01).
13.4.8 PORTC – Port C Data Register Bit 13.4.9 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC – Port C Data Direction Register Bit 13.4.
13.4.16 PINE – Port E Input Pins Address Bit 7 6 5 4 3 2 1 0 PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 0x0C (0x2C) 13.4.17 PORTF – Port F Data Register Bit 7 6 5 4 3 2 1 0 0x11 (0x31) PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.4.
13.4.24 DDRH – Port H Data Direction Register Bit 7 6 5 4 3 2 1 0 DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x101) 13.4.25 PINH – Port H Input Pins Address Bit 7 6 5 4 3 2 1 0 PINH5 PINH5 PINH5 PINH4 PINH3 PINGH PINH1 PINH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A (0x100) 13.4.
13.4.32 PORTL – Port L Data Register Bit 7 6 5 4 3 2 1 0 PORTL7 PORTL6 PORTL5 PORTL4 PORTL3 PORTL2 PORTL1 PORTL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x10B) 13.4.33 DDRL – Port L Data Direction Register Bit 7 6 5 4 3 2 1 0 DDL7 DDL6 DDL5 DDL4 DDL3 DDL2 DDL1 DDL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x10A) 13.4.
14. Interrupts This section describes the specifics of the interrupt handling as performed in ATmega640/1280/1281/2560/2561. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 17. 14.1 Interrupt Vectors in ATmega640/1280/1281/2560/2561 Table 14-1. Reset and Interrupt Vectors Vector No.
Table 14-1. Vector No.
Reset and Interrupt Vectors Placement(1) Table 14-2. BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x0000 0x0002 1 1 0x0000 Boot Reset Address + 0x0002 0 0 Boot Reset Address 0x0002 0 1 Boot Reset Address Boot Reset Address + 0x0002 Note: 1. The Boot Reset Address is shown in Table 29-7 on page 320 through Table 29-15 on page 322. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
0x002 8 jmp TIM1_OVF ; Timer1 Overflow Handler 0x002 A jmp TIM0_COMPA ; Timer0 CompareA Handler 0x002 C jmp TIM0_COMPB ; Timer0 CompareB Handler 0x002 E jmp TIM0_OVF ; Timer0 Overflow Handler 0x003 0 jmp SPI_STC ; SPI Transfer Complete Handler 0x003 2 jmp USART0_RXC ; USART0 RX Complete Handler 0x003 4 jmp USART0_UDRE ; USART0,UDR Empty Handler 0x003 6 jmp USART0_TXC ; USART0 TX Complete Handler 0x003 8 jmp ANA_COMP ; Analog Comparator Handler 0x003 A jmp ADC ; ADC Con
0x006 2 jmp TIM5_COMPC ; Timer5 CompareC Handler 0x006 4 jmp TIM5_OVF ; Timer5 Overflow Handler 0x006 6 jmp USART2_RXC ; USART2 RX Complete Handler 0x006 8 jmp USART2_UDRE ; USART2,UDR Empty Handler 0x006 A jmp USART2_TXC ; USART2 TX Complete Handler 0x006 C jmp USART3_RXC ; USART3 RX Complete Handler 0x006 E jmp USART3_UDRE ; USART3,UDR Empty Handler 0x007 0 jmp USART3_TXC ; USART3 TX Complete Handler ldi r16, high(RAMEND) ; Main program start 0x007 3 out SPH,r16 ; Set
When the BOOTRST Fuse is programmed and the Boot section size set to 8Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org 0x0002 0x00002 jmp EXT_INT0 ; IRQ0 Handler 0x00004 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x00070 jmp USART3_TXC ; USART3 TX Complete Handler ; .
14.3 Moving Interrupts Between Application and Boot Section The MCU Control Register controls the placement of the Interrupt Vector table, see Code Example below. For more details, see “Reset and Interrupt Handling” on page 17.
14.4 14.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash.
15. External Interrupts The External Interrupts are triggered by the INT7:0 pin or any of the PCINT23:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT23:0 pins are configured as outputs. This feature provides a way of generating a software interrupt.
15.2 15.2.1 Register Description EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control.
15.2.2 EICRB – External Interrupt Control Register B Bit 7 6 5 4 3 2 1 0 ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x6A) EICRB • Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set.
15.2.4 EIFR – External Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 IINTF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x1C (0x3C) EIFR • Bits 7:0 – INTF7:0: External Interrupt Flags 7 - 0 When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one).
15.2.6 PCIFR – Pin Change Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x1B (0x3B) – – – – – PCIF2 PCIF1 PCIF0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCIFR • Bit 2 – PCIF2: Pin Change Interrupt Flag 1 When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
15.2.9 PCMSK0 – Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 (0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK0 • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin.
16. 8-bit Timer/Counter0 with PWM Features • • • • • • • 16.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
16.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin.
Figure 16-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn Control Logic Edge Detector clkTn Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value.
Figure 16-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately. 16.
16.7 Modes of Operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00).
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Figure 16-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
16.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 16-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 16-8.
Figure 16-11.
16.9 16.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to.
Table 16-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected WGM02 = 1: Toggle OC0A on Compare Match 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting 1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set.
Table 16-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 16-7. COM0B1 COM0B0 Description 0 0 Normal port operation, OC0B disconnected 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting Note: 1.
16.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
Table 16-9. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge 1 1 1 External clock source on T0 pin.
16.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6E) – – – – – OCIE0B OCIE0A TOIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 • Bits 7:3, 0 – Res: Reserved Bits These bits are reserved bits and will always read as zero.
SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 16-8, “Waveform Generation Mode Bit Description” on page 128.
17. 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5) 17.1 Features • • • • • • • • • • • 17.
Figure 17-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic TCLK Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCFnA (Int.Req.) Waveform Generation = OCnA OCRnA OCFnB (Int.Req.) Fixed TOP Values Waveform Generation DATABUS = OCnB OCRnB OCFnC (Int.Req.) Waveform Generation = OCnC OCRnC ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 17.2.
its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkTn). The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C). See “Output Compare Units” on page 141.
Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. See “About Code Examples” on page 10. The assembly code example returns the TCNTn value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations.
Assembly Code Example(1) TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1.
The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
17.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 17-2 shows a block diagram of the counter and its surroundings. Figure 17-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
17.6 Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied.
17.6.1 Input Capture Trigger Source The main trigger source for the input capture unit is the Input Capture Pin (ICPn). Timer/Counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. The Analog Comparator is selected as trigger source by setting the analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture.
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that is, counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 17-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = n for Timer/Counter n), and the “x” indicates Output Compare unit (A/B/C).
17.7.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or toggled). 17.7.
Figure 17-5. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
Waveform Generation Mode Bit Description(1) Table 17-2.
counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 17-6. The counter value (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 17-6.
mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer feature.
on Figure 17-8 on page 149. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. Figure 17-8.
rements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Figure 17-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
17.10 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 17-10 shows a timing diagram for the setting of OCFnx. Figure 17-10.
Figure 17-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. Figure 17-12.
17.11 Register Description 17.11.1 TCCR1A – Timer/Counter 1 Control Register A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x80) 17.11.
• Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 17-2 on page 145. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes.
17.11.5 TCCR1B – Timer/Counter 1 Control Register B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x81) 17.11.6 TCCR3B – Timer/Counter 3 Control Register B Bit 7 6 5 4 3 2 1 0 ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x91) 17.11.
• Bit 2:0 – CSn2:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 17-10 and Figure 17-11 on page 152. Table 17-6. Clock Select Bit Description CSn2 CSn1 CSn0 Description 0 0 0 No clock source.
FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB/FOCnB bits are always read as zero. • Bit 4:0 – Reserved Bits These bits are reserved for future use.
17.11.17 OCR1AH and OCR1AL – Output Compare Register 1 A Bit 7 6 5 4 3 (0x89) OCR1A[15:8] (0x88) OCR1A[7:0] 2 1 0 OCR1AH OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 17.11.18 OCR1BH and OCR1BL – Output Compare Register 1 B Bit 7 6 5 4 (0x8B) OCR1B[15:8] (0x8A) OCR1B[7:0] OCR1BH OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 17.11.
17.11.24 OCR4BH and OCR4BL – Output Compare Register 4 B Bit 7 6 5 4 3 (0xAA) OCR4B[15:8] (0xAB) OCR4B[7:0] 2 1 0 OCR4BH OCR4BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 17.11.25 OCR4CH and OCR4CL –Output Compare Register 4 C Bit 7 6 5 4 (0xAD) OCR4C[15:8] (0xAC) OCR4C[7:0] OCR4CH OCR4CL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 17.11.
17.11.30 ICR3H and ICR3L – Input Capture Register 3 Bit 7 6 5 4 3 (0x97) ICR3[15:8] (0x96) ICR3[7:0] 2 1 0 ICR3H ICR3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 17.11.31 ICR4H and ICR4L – Input Capture Register 4 Bit 7 6 5 4 (0xA7) ICR4[15:8] (0xA6) ICR4[7:0] ICR4H ICR4L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 17.11.
17.11.36 TIMSK5 – Timer/Counter 5 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x73) – – ICIE5 – OCIE5C OCIE5B OCIE5A TOIE5 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK5 • Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled.
17.11.40 TIFR5 – Timer/Counter5 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x1A (0x3A) – – ICF5 – OCF5C OCF5B OCF5A TOV5 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR5 • Bit 5 – ICFn: Timer/Countern, Input Capture Flag This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register (ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the counter reaches the TOP value.
18. Timer/Counter 0, 1, 3, 4, and 5 Prescaler Timer/Counter 0, 1, 3, 4, and 5 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1, 3, 4, or 5. 18.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
18.4 Register Description 18.4.1 GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode.
19. Output Compare Modulator (OCM1C0A) 19.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details about these Timer/Counters see “Timer/Counter 0, 1, 3, 4, and 5 Prescaler” on page 164 and “8-bit Timer/Counter2 with PWM and Asynchronous Operation” on page 169. Figure 19-1.
19.2.1 Timing example Figure 19-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 19-3.
20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • • • • • • • Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 17-12 on page 153 For the actual placement of I/O pins, see “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold.
20.1.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section.
Figure 20-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count clear TCNTn clk Tn Control Logic Prescaler T/C Oscillator direction TOSC2 bottom top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value.
20.4.1 Normal Mode The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero.
20.4.3 Fast PWM Mode Figure 20-4. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.
frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 20-5.
At the very start of period 2 in Figure 20-5 on page 174 OCnx has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. 20.5 • OCR2A changes its value from MAX, like in Figure 20-5 on page 174. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting compare match.
20.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or toggled). 20.5.
Figure 20-7. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
Figure 20-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 20-9 shows the same timing data, but with the prescaler enabled. Figure 20-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 20-10 shows the setting of OCF2A in all modes except CTC mode. Figure 20-10.
Figure 20-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 20-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCRnx OCFnx 20.8 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken.
1. Write a value to TCCR2x, TCNT2, or OCR2x. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or ADC Noise Reduction mode. • When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize.
The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2.
20.10 Register Description 20.10.1 TCCR2A –Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to.
Table 20-4. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected WGM22 = 1: Toggle OC2A on Compare Match 1 0 Clear OC2A on Compare Match when up-counting Set OC2A on Compare Match when down-counting 1 1 Set OC2A on Compare Match when up-counting Clear OC2A on Compare Match when down-counting Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set.
Table 20-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 20-7. Compare Output Mode, Phase Correct PWM Mode(1) COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected 0 1 Reserved 1 0 Clear OC2B on Compare Match when up-counting Set OC2B on Compare Match when down-counting 1 1 Set OC2B on Compare Match when up-counting Clear OC2B on Compare Match when down-counting Note: 1.
20.10.2 TCCR2B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 FOC2A FOC2B – – WGM22 CS22 CS21 CS20 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB1) TCCR2B • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
Table 20-9. Clock Select Bit Description (Continued) CS22 CS21 CS20 Description 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 20.10.
20.10.6 ASSR – Asynchronous Status Register Bit 7 6 5 4 3 2 1 0 (0xB6) – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal.
20.10.7 TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x70) – – – – – OCIE2B OCIE2A TOIE2 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK2 • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled.
20.10.9 GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 1 – PSRASY: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware.
21. SPI – Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega640/1280/1281/2560/2561 and peripheral devices or between several AVR devices.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 21-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 21-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 72. Table 21-1. Pin Note: SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input 1.
Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
21.1 21.1.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
Figure 21-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 21-4.
21.2 21.2.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in Table 21-5. Table 21-5. 21.2.
21.2.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
22. USART 22.1 Features • • • • • • • • • • • • 22.
Figure 22-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1.
Figure 22-2 shows a block diagram of the clock generation logic. Figure 22-2. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 1 UCPOL txclk UMSEL 1 xcko DDR_XCK 1 0 rxclk Signal description: 22.3.1 txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
Table 22-1.
22.3.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn) is changed. Figure 22-3. Synchronous Mode XCKn Timing.
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The USART Parity mode (UPMn1:0) bits enable and set the type of parity bit.
Assembly Code Example(1) USART_Init: ; Set baud rate sts UBRRnH, r17 sts UBRRnL, r16 ldi r16, (1<
22.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
22.6.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
UDREn is cleared by writing UDRn. When interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer.
Assembly Code Example(1) USART_Receive: ; Wait for data to be received lds r17, UCSRnA sbrs r17, RXCn rjmp USART_Receive ; Get and return received data from buffer lds r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
Assembly Code Example(1) USART_Receive: ; Wait for data to be received lds r17, UCSRnA sbrs r17, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer lds r18, UCSRnA lds r17, UCSRnB lds r16, UDRn ; If error, return -1 andi r18,(1<
22.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
22.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost. 22.7.
Figure 22-5. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 22-7 on page 214. For Double Speed mode the first low level must be delayed to (B).
Table 22-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max. total error (%) Recommended max. receiver error (%) 5 94.12 105.66 +5.66/-5.88 ±2.5 6 94.92 104.92 +4.92/-5.08 ±2.0 7 95.52 104.35 +4.35/-4.48 ±1.5 8 96.00 103.90 +3.90/-4.00 ±1.5 9 96.39 103.53 +3.53/-3.61 ±1.5 10 96.70 103.23 +3.23/-3.30 ±1.
4. The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames. 5. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and waits for a new address frame from master. The process then repeats from 2.
22.10 Register Description The following section describes the USART’s registers. 22.10.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
22.10.2 UCSRnA – USART Control and Status Register A Bit 7 6 5 4 3 2 1 0 RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn Read/Write R R/W R R R R R/W R/W Initial Value 0 0 1 0 0 0 0 0 UCSRnA • Bit 7 – RXCn: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (that is, does not contain any unread data).
22.10.3 UCSRnB – USART Control and Status Register n B Bit 7 6 5 4 3 2 1 0 RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 UCSRnB • Bit 7 – RXCIEn: RX Complete Interrupt Enable n Writing this bit to one enables interrupt on the RXCn Flag.
22.10.4 UCSRnC – USART Control and Status Register n C Bit 7 6 5 4 3 2 1 0 UMSELn1 UMSELn0 UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRnC • Bits 7:6 – UMSELn1:0 USART Mode Select These bits select the mode of operation of the USARTn as shown in Table 22-4. Table 22-4.
Table 22-7. UCSZn Bits Settings UCSZn2 UCSZn1 UCSZn0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 22-8. 22.10.
22.11 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 22-9 to Table 22-12 on page 226. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
Table 22-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud Rate [bps] UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4K 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.
Table 22-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 11.0592MHz fosc = 8.0000MHz fosc = 14.7456MHz Baud Rate [bps] UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4K 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.
Table 22-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz Baud Rate [bps] UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4K 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.
23. USART in SPI Mode The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the following features: • • • • • • • • 23.
correctly. Preferably the DDR_XCKn should be set up before the USART in MSPIM is enabled (that is, TXENn and RXENn bit set to one). The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The baud rate or UBRRn setting can therefore be calculated using the same equations, see Table 23-1. Table 23-1.
23.4 Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: • 8-bit data with MSB first • 8-bit data with LSB first A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly.
The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume polling (no interrupts enabled). The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode.
23.5 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, that is, the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
Assembly Code Example(1) USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDRn,r16 ; Wait for data to be received USART_MSPIM_Wait_RXCn: sbis UCSRnA, RXCn rjmp USART_MSPIM_Wait_RXCn ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
23.6.2 UCSRnA – USART MSPIM Control and Status Register n A • Bit 7 6 5 4 3 2 1 RXCn TXCn UDREn - - - - 0 - Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 1 1 0 UCSRnA • Bit 7 - RXCn: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (that is, does not contain any unread data).
23.6.3 UCSRnB – USART MSPIM Control and Status Register n B Bit 7 6 5 4 3 2 1 RXCIEn TXCIEn UDRIE RXENn TXENn - - 0 - Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 1 1 0 UCSRnB • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag.
23.6.4 UCSRnC – USART MSPIM Control and Status Register n C Bit 7 6 5 4 3 2 1 0 UMSELn1 UMSELn0 - - - UDORDn UCPHAn UCPOLn Read/Write R/W R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRnC • Bit 7:6 - UMSELn1:0: USART Mode Select These bits select the mode of operation of the USART as shown in Table 23-3. See “UCSRnC – USART Control and Status Register n C” on page 221 for full description of the normal USART operation.
24. 2-wire Serial Interface 24.1 Features • • • • • • • • • • 24.
24.2.2 Electrical Interconnection As depicted in Figure 24-1 on page 236, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wiredAND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
Figure 24-3. START, REPEATED START and STOP conditions SDA SCL START 24.3.3 STOP REPEATED START START STOP Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
Figure 24-5. Data Packet Format Data MSB Data LSB ACK 8 9 Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 SLA+R/W 24.3.5 7 STOP, REPEATED START or Next Data Byte Data Byte Combining Address and Data Packets into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal.
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period.
Figure 24-8. Arbitration Between Two Masters START Master A Loses Arbitration, SDAA SDA SDA from Master A SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
Figure 24-9. Overview of the TWI Module SCL Spike Filter Slew-rate Control Spike Filter Bus Interface Unit START / STOP Control Spike Suppression Arbitration detection Address/Data Shift Register (TWDR) Address Match Unit Address Register (TWAR) Address Comparator 24.5.
• TWBR = Value of the TWI Bit Rate Register • TWPS = Value of the prescaler bits in the TWI Status Register Note: 24.5.3 Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See “2-wire Serial Interface Characteristics” on page 361 for value of pull-up resistor. Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware.
24.6 Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer.
4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the address packet has successfully been sent. The status code will also reflect whether a Slave acknowledged the packet or not. 5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected.
Assembly Code Example 1 ldi r16, (1<
24.7 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes free.
Table 24-2.
Figure 24-12.
Figure 24-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
Table 24-3.
Figure 24-14. Formats and States in the Master Receiver Mode MR Successfull reception from a slave receiver S SLA R A DATA A $40 $08 DATA $50 A P $58 Next transfer started with a repeated start condition RS SLA R $10 Not acknowledge received after the slave address A W P $48 MT Arbitration lost in slave address or data byte A or A Other master continues $38 Arbitration lost and addressed as slave A $68 From slave to master 24.7.
The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address.
Table 24-4.
Figure 24-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 TWA4 value TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
Table 24-5.
it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted. Table 24-6.
Figure 24-20. An Arbitration Example VCC Device 1 Device 2 Device 3 MASTER TRANSMITTER MASTER TRANSMITTER SLAVE RECEIVER ........ Device n R1 R2 SDA SCL Several different scenarios may arise during arbitration, as described below: • Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention. • Two or more masters are accessing the same Slave with different data or direction bit.
24.9 24.9.1 Register Description TWBR – TWI Bit Rate Register Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB8) TWBR • Bits 7:0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
• Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.
To calculate bit rates, see “Bit Rate Generator Unit” on page 242. The value of TWPS1:0 is used in the equation. 24.9.4 TWDR – TWI Data Register Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 (0xBB) TWDR In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received.
24.9.6 TWAMR – TWI (Slave) Address Mask Register Bit 7 6 5 4 (0xBD) 3 2 1 0 TWAM[6:0] – Read/Write R/W R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TWAMR • Bits 7:1 – TWAM: TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR).
25. AC – Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
Table 25-1. 25.2 25.2.
• Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set.
26. ADC – Analog to Digital Converter 26.1 Features • • • • • • • • • • • • • • • 10-bit Resolution 1 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 13µs - 260µs Conversion Time Up to 76.9kSPS (Up to 15kSPS at Maximum Resolution) 16 Multiplexed Single Ended Input Channels 14 Differential input channels 4 Differential Input Channels with Optional Gain of 10× and 200× Optional Left Adjustment for ADC Result Readout 0V - VCC ADC Input Voltage Range 2.7V - VCC Differential ADC Voltage Range Selectable 2.
Figure 26-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] ADFR ADSC ADC[9:0] ADIF ADPS[2:0] ADEN MUX[5] DIFF / GAIN SELECT CHANNEL SELECTION INTERNAL REFERENCE (1.1V/2.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL.
this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. Prescaling and Conversion Timing Figure 26-3.
Figure 26-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 2 12 13 14 16 15 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Conversion Complete Sample & Hold MUX and REFS Update Figure 26-5.
Figure 26-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete Table 26-1. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 1.5/2.
26.5 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC.
AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant voltmeter.
Figure 26-8. Analog Input Circuitry IIH ADCn 1..100kΩ CS/H= 14pF IIL VCC/2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the ground plane, and keep them well away from high-speed switching digital tracks. 2.
Figure 26-10. ADC Power Connections, ATmega640/1280/2560 PJ7 79 VCC 80 GND 81 (ADC15/PCINT23) PK7 82 (ADC14/PCINT22) PK6 83 (ADC13/PCINT21) PK5 84 (ADC12/PCINT20) PK4 85 (ADC11/PCINT19) PK3 86 (ADC10/PCINT18) PK2 87 (ADC9/PCINT17) PK1 88 (ADC8/PCINT16) PK0 89 (ADC7/TDI) PF7 90 (ADC6/TDO) PF6 91 (ADC5/TMS) PF5 92 (ADC4/TCK) PF4 93 (ADC3) PF3 94 (ADC2) PF2 95 (ADC1) PF1 96 (ADC0) PF0 97 AREF 98 10μΗ GND 99 AVCC 100 Ground Plane 26.6.
Figure 26-11. Offset Error Output Code Ideal ADC Actual ADC Offset Error • VREF Input Voltage Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB. Figure 26-12.
Figure 26-13. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 26-14.
26.7 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 26-3 on page 281 and Table 26-4 on page 282). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
Table 26-2. Correlation Between Input Voltage and Output Codes VADCn Read Code Corresponding Decimal Value VADCm + VREF / GAIN 0x1FF 511 VADCm + 0.999 VREF / GAIN 0x1FF 511 VADCm + 0.998 VREF / GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF / GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF / GAIN 0x3FF -1 ... ... ... VADCm - 0.999 VREF / GAIN 0x201 -511 VADCm - VREF / GAIN 0x200 -512 Example: ADMUX = 0xFB (ADC3 - ADC2, 10× gain, 2.56V reference, left adjusted result).
• Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “ADCL and ADCH – The ADC Data Register” on page 286.
Table 26-4.
Table 26-4.
26.8.3 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
26.8.4 ADCL and ADCH – The ADC Data Register 26.8.4.1 ADLAR = 0 Bit 15 14 13 12 11 10 9 8 (0x79) – – – – – – ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value 26.8.4.
26.8.5 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – ACME – – MUX5 ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 7 – Res: Reserved Bit This bit is reserved for future use. To ensure compatibility with future devices, this bit must be written to zero when ADCSRB is written.
26.8.7 DIDR2 – Digital Input Disable Register 2 Bit 7 6 5 4 3 2 1 0 ADC15D ADC14D ADC13D ADC12D ADC11D ADC10D ADC9D ADC8D Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7D) DIDR2 • Bit 7:0 – ADC15D:ADC8D: ADC15:8 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
27. JTAG Interface and On-chip Debug System 27.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
Figure 27-1. Block Diagram I/O PORT 0 DEVICE BOUNDARY BOUNDARY SCAN CHAIN TDI TDO TCK TMS JTAG PROGRAMMING INTERFACE TAP CONTROLLER AVR CPU INSTRUCTION REGISTER ID REGISTER M U X FLASH MEMORY Address Data BREAKPOINT UNIT BYPASS REGISTER INTERNAL SCAN CHAIN PC Instruction FLOW CONTROL UNIT DIGITAL PERIPHERAL UNITS ANALOG PERIPHERIAL UNITS Analog inputs BREAKPOINT SCAN CHAIN ADDRESS DECODER JTAG / AVR CORE COMMUNICATION INTERFACE OCD STATUS AND CONTROL Control & Clock lines I/O PORT n 27.
Figure 27-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 27.3.1 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system.
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – ShiftDR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in when this state is left by setting TMS high.
execution of Assembly programs assembled with Atmel Corporation’s AVR Assembler and C programs compiled with third party vendors’ compilers. AVR Studio runs under Microsoft® Windows® 95/98/2000 and Microsoft Windows NT. For a full description of the AVR Studio, refer to the AVR Studio User Guide. Only highlights are presented in this document. All necessary execution commands are available in AVR Studio, both on source level and on disassembly level.
27.8 Bibliography For more information about general Boundary-scan, the following literature can be consulted: 27.9 27.9.1 • IEEE: IEEE Std. 1149.1-1990.
28. IEEE 1149.1 (JTAG) Boundary-scan 28.1 Features • • • • • 28.2 JTAG (IEEE std. 1149.
28.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. 28.3.2 Device Identification Register Figure 28-1 shows the structure of the Device Identification Register. Figure 28-1.
Figure 28-2. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 28.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See “Boundary-scan Chain” on page 298 for a complete description. 28.
28.4.3 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
When JTAG IR contains EXTEST or SAMPLE_PRELOAD the clock is not sent out on the port pins even if the CKOUT fuse is programmed. Even though the clock is output when the JTAG IR contains SAMPLE_PRELOAD, the clock is not sampled by the boundary scan. Figure 28-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
Figure 28-4. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR RESET OCxn WDx Q Pxn ODxn D PORTxn Q CLR WRx IDxn DATA BUS RDx RESET SLEEP RRx SYNCHRONIZER D Q L Q D RPx Q PINxn Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 28.5.
28.6 28.6.1 Boundary-scan Related Register in I/O Memory MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bits 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled.
Table 28-1. ATmega640/1280/2560 Boundary-scan Order Bit Number Signal Name 164 PG5.Data 163 PG5.Control 162 PE0.Data 161 PE0.Control 160 PE1.Data 159 PE1.Control 158 PE2.Data 157 PE2.Control 156 PE3.Data 155 PE3.Control 154 PE4.Data 153 PE4.Control 152 PE5.Data 151 PE5.Control 150 PE6.Data 149 PE6.Control 148 PE7.Data 147 PE7.Control 146 PH0.Data 145 PH0.Control 144 PH1.Data 143 PH1.Control 142 PH2.Data 141 PH2.Control 140 PH3.Data 139 PH3.
Table 28-1. ATmega640/1280/2560 Boundary-scan Order (Continued) Bit Number Signal Name 132 PB0.Data 131 PB0.Control 130 PB1.Data 129 PB1.Control 128 PB2.Data 127 PB2.Control 126 PB3.Data 125 PB3.Control 124 PB4.Data 123 PB4.Control 122 PB5.Data 121 PB5.Control 120 PB6.Data 119 PB6.Control 118 PB7.Data 117 PB7.Control 116 PH7.Data 115 PH7.Control 114 PG3.Data 113 PG3.Control 112 PG4.Data 111 PG4.Control 110 RSTT 109 PL0.Data 108 PL0.Control 107 PL1.
Table 28-1. ATmega640/1280/2560 Boundary-scan Order (Continued) Bit Number Signal Name 104 PL2.Control 103 PL3.Data 102 PL3.Control 101 PL4.Data 100 PL4.Control 99 PL5.Data 98 PL5.Control 97 PL6.Data 96 PL6.Control 95 PL7.Data 94 PL7.Control 93 PD0.Data 92 PD0.Control 91 PD1.Data 90 PD1.Control 89 PD2.Data 88 PD2.Control 87 PD3.Data 86 PD3.Control 85 PD4.Data 84 PD4.Control 83 PD5.Data 82 PD5.Control 81 PD6.Data 80 PD6.Control 79 PD7.Data 78 PD7.
Table 28-1. ATmega640/1280/2560 Boundary-scan Order (Continued) Bit Number Signal Name 68 PC2.Control 67 PC3.Data 66 PC3.Control 65 PC4.Data 64 PC4.Control 63 PC5.Data 62 PC5.Control 61 PC6.Data 60 PC6.Control 59 PC7.Data 58 PC7.Control 57 PJ0.Data 56 PJ0.Control 55 PJ1.Data 54 PJ1.Control 53 PJ2.Data 52 PJ2.Control 51 PJ3.Data 50 PJ3.Control 49 PJ4.Data 48 PJ4.Control 47 PJ5.Data 46 PJ5.Control 45 PJ6.Data 44 PJ6.Control 43 PG2.Data 42 PG2.
Table 28-1. ATmega640/1280/2560 Boundary-scan Order (Continued) Bit Number Signal Name 32 PA3.Control 31 PA2.Data 30 PA2.Control 29 PA1.Data 28 PA1.Control 27 PA0.Data 26 PA0.Control 25 PJ7.Data 24 PJ7.Control 23 PK7.Data 22 PK7.Control 21 PK6.Data 20 PK6.Control 19 PK5.Data 18 PK5.Control 17 PK4.Data 16 PK4.Control 15 PK3.Data 14 PK3.Control 13 PK2.Data 12 PK2.Control 11 PK1.Data 10 PK1.Control 9 PK0.Data 8 PK0.Control 7 PF3.Data 6 PF3.
Table 28-2. ATmega1281/2561 Boundary-scan Order Bit Number Signal Name 100 PG5.Data 99 PG5.Control 98 PE0.Data 97 PE0.Control 96 PE1.Data 95 PE1.Control 94 PE2.Data 93 PE2.Control 92 PE3.Data 91 PE3.Control 90 PE4.Data 89 PE4.Control 88 PE5.Data 87 PE5.Control 86 PE6.Data 85 PE6.Control 84 PE7.Data 83 PE7.Control 82 PB0.Data 81 PB0.Control 80 PB1.Data 79 PB1.Control 78 PB2.Data 77 PB2.Control 76 PB3.Data 75 PB3.Control 74 PB4.Data 73 PB4.
Table 28-2. ATmega1281/2561 Boundary-scan Order (Continued) Bit Number Signal Name 65 PG3.Control 64 PG4.Data 63 PG4.Control 62 RSTT 61 PD0.Data 60 PD0.Control 59 PD1.Data 58 PD1.Control 57 PD2.Data 56 PD2.Control 55 PD3.Data 54 PD3.Control 53 PD4.Data 52 PD4.Control 51 PD5.Data 50 PD5.Control 49 PD6.Data 48 PD6.Control 47 PD7.Data 46 PD7.Control 45 PG0.Data 44 PG0.Control 43 PG1.Data 42 PG1.Control 41 PC0.Data 40 PC0.Control 39 PC1.Data 38 PC1.
Table 28-2. ATmega1281/2561 Boundary-scan Order (Continued) Bit Number Signal Name 29 PC6.Data 28 PC6.Control 27 PC7.Data 26 PC7.Control 25 PG2.Data 24 PG2.Control 23 PA7.Data 22 PA7.Control 21 PA6.Data 20 PA6.Control 19 PA5.Data 18 PA5.Control 17 PA4.Data 16 PA4.Control 15 PA3.Data 14 PA3.Control 13 PA2.Data 12 PA2.Control 11 PA1.Data 10 PA1.Control 9 PA0.Data 8 PA0.Control 7 PF3.Data 6 PF3.Control 5 PF2.Data 4 PF2.Control 3 PF1.Data 2 PF1.
29. Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
• When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update. 29.3.
Figure 29-2.
Table 29-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or (E)LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. Note: Protection 3 0 0 SPM is not allowed to write to the Application section, and (E)LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
29.5 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is implementation dependent. Note that the RAMPZ register is only implemented when the program space is larger than 64Kbytes.
29.6 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
ware. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in “Interrupts” on page 101. 29.6.5 Consideration While Updating BLS Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11 unprogrammed.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When an (E)LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. 2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level.
; execute Page Write subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcrval, (1<
ATmega640 Boot Loader Parameters In Table 29-7 through Table 29-9 on page 320, the parameters used in the description of the Self-Programming are given. Boot Reset Address (Start Boot Loader Section) End Application Section Boot Loader Flash Section Pages Boot Size BOOTSZ0 Appli-cation Flash Section Boot Size Configuration, ATmega640(1) Table 29-7. BOOTSZ1 29.6.
ATmega1280/1281 Boot Loader Parameters In Table 29-10 and Table 29-11, the parameters used in the description of the Self-Programming are given. Boot Reset Address (Start Boot Loader Section) End Application Section Boot Loader Flash Section Appli-cation Flash Section Pages Boot Size BOOTSZ0 Table 29-10. Boot Size Configuration, ATmega1280/1281(1) BOOTSZ1 29.6.
ATmega2560/2561 Boot Loader Parameters In Table 29-13 through Table 29-15, the parameters used in the description of the Self-Programming are given. Boot Reset Address (Start Boot Loader Section) End Application Section Boot Loader Flash Section Appli-cation Flash Section Pages Boot Size BOOTSZ0 Table 29-13. Boot Size Configuration, ATmega2560/2561(1) BOOTSZ1 29.6.
29.7 29.7.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
• Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed.
30. Memory Programming 30.1 Program And Data Memory Lock Bits The ATmega640/1280/1281/2560/2561 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 30-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 30-1.
Lock Bit Protection Modes(1)(2) (Continued) Table 30-2. Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. Notes: 30.2 Protection Type 3 0 0 SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
Table 30-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled) (1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
30.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. For the ATmega640/1280/1281/2560/2561 the signature bytes are given in Table 30-6. Table 30-6. Device and JTAG ID Signature Bytes Address 30.
Figure 30-1. Parallel Programming(1) +5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12V RESET BS2 PA0 VCC +5V AVCC DATA PB7 - PB0 XTAL1 GND Note: 1. Unused Pins should be left floating. Table 30-9.
Table 30-11. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 30-12. XA1 and XA0 Enoding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS2 and BS1) 0 1 Load Data (High or Low data byte for Flash determined by BS1) 1 0 Load Command 1 1 No Action, Idle Table 30-13. Command Byte Bit Encoding Command Byte 30.7 30.7.
30.7.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. 30.7.
D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. E. Latch Data 1. Set BS1 to “1”. This selects high data byte. 2. Give PAGEL a positive pulse. This latches the data bytes. See Figure 30-3 on page 333 for signal waveforms. F.
Figure 30-2. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 30-7 on page 328. Figure 30-3. Programming the Flash Waveforms(1) F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G H ADDR. HIGH ADDR. EXT.
1. Set BS2, BS1 to “00”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (see Figure 30-4 for signal waveforms). Figure 30-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B C ADDR. LOW DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 30.7.
30.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to “Programming the Flash” on page 331 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS2, BS1 to “01”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2, BS1 to “00”. This selects low data byte. 30.7.
30.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 331 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4. Set OE to “0”, and BS2, BS1 to “10”.
30.7.15 Parallel Programming Characteristics Figure 30-7. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 30-8.
Table 30-14. Parallel Programming Characteristics, VCC = 5V ±10% Symbol Parameter Min VPP Programming Enable Voltage 11.
30.8.1 Serial Programming Pin Mapping Table 30-15. Pin Mapping Serial Programming Symbol Pins (TQFP-100) Pins (TQFP-64) I/O Description PDI PB2 PE0 I Serial Data in PDO PB3 PE1 O Serial Data out SCK PB1 PB1 I Serial Clock Figure 30-10. Serial Programming and Verify(1) +1.8V - 5.5V VCC +1.8V - 5.5V(2) PDI AVCC PDO SCK XT AL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.
3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time.
Table 30-17.
Figure 30-11. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Adr MSB A Byte 3 Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr LSB Bit 15 B Adr MSB Byte 3 Adrr LSB B Bit 15 B 0 Byte 4 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 30.8.
while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose. During programming the clock frequency of the TCK Input must be less than the maximum frequency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input into a sufficiently low frequency.
30.9.2 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data Register. Note that the reset will be active as long as there is a logic “one” in the Reset Chain. The output from this chain is not latched. The active states are: • 30.9.
30.9.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section “Programming Specific JTAG Instructions” on page 343. The Data Registers relevant for programming operations are: 30.9.8 • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register Reset Register The Reset Register is a Test Data Register used to reset the part during programming.
Figure 30-15.
Table 30-18. JTAG Programming Instruction Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
Table 30-18. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d.
Table 30-18. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8e. Read Lock Bits(9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 8f.
Figure 30-16. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 30.9.
Figure 30-17. Flash Data Byte Register STROBES TDI State Machine ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate through the TAP controller automatically feeds the state machine for the Flash Data Byte Register with sufficient number of clock pulses to complete its operation transparently for the user.
30.9.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 351. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address Extended High byte using programming instruction 2b. 4. Load address High byte using programming instruction 2c. 5. Load address Low byte using programming instruction 2d. 6. Load data using programming instructions 2e, 2f and 2g. 7.
6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. 30.9.18 Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed, see “Performing Chip Erase” on page 351. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address High byte using programming instruction 4b. 4. Load address Low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6.
30.9.22 Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8e. To only read Fuse High byte, use programming instruction 8b. To only read Fuse Low byte, use programming instruction 8c. To only read Lock bits, use programming instruction 8d. 30.9.23 Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2.
31. Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition (5) Min. Typ. Max. Active 1MHz, VCC = 2V (ATmega640/1280/2560/1V) 0.5 0.8 Active 4MHz, VCC = 3V (ATmega640/1280/2560/1L) 3.2 5 Active 8MHz, VCC = 5V (ATmega640/1280/1281/2560/2561) 10 14 Idle 1MHz, VCC = 2V (ATmega640/1280/2560/1V) 0.14 0.22 Idle 4MHz, VCC = 3V (ATmega640/1280/2560/1L) 0.7 1.1 Idle 8MHz, VCC = 5V (ATmega640/1280/1281/2560/2561) 2.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Values with “PRR1 – Power Reduction Register 1” on page 56 enabled (0xFF). 31.2 Speed Grades Maximum frequency is depending on VCC. As shown in Figure 31-1 trough Figure 31-4 on page 358, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. 31.2.1 8MHz Figure 31-1. Maximum Frequency vs.
31.2.2 16MHz Figure 31-3. Maximum Frequency vs. VCC, ATmega640/ATmega1280/ATmega1281 16 MHz 8 MHz Safe Operating Area 2.7V 4.5V 5.5V Figure 31-4. Maximum Frequency vs. VCC, ATmega2560/ATmega2561 16 MHz Safe Operating Area 4.5V 5.
31.3 31.3.1 Clock Characteristics Calibrated Internal RC Oscillator Accuracy Table 31-1. Calibration Accuracy of Internal RC Oscillator Factory Calibration Frequency VCC 8.0MHz 3V Temperature Calibration Accuracy 25C ±10% -40C - 85C ±1% (1) User Calibration Notes: 31.3.2 1.8V - 5.5V 2.7V - 5.5V(2) 7.3MHz - 8.1MHz 1. Voltage range for ATmega640V/1281V/1280V/2561V/2560V. 2. Voltage range for ATmega640/1281/1280/2561/2560. External Clock Drive Waveforms Figure 31-5.
31.5 System and Reset Characteristics Table 31-3. Symbol Parameter Condition Min Typ 0.2VCC VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin Max Units 0.9VCC V 2.5 µs Brown-out Detector Hysteresis 50 mV tBOD Min Pulse Width on Brown-out Reset 2 µs VBG Bandgap reference voltage VCC=2.7V, TA= 25C tBG Bandgap reference start-up time IBG Bandgap reference current consumption VHYST Note: 31.5.
31.5.2 Enhanced Power-On Reset This implementation of power-on reset exists in newer versions of ATmega640/1280/1281/2560/2561. The table below describes the characteristics of this power-on reset and it is valid for the following devices only: • ATmega640: revision B and newer • ATmega1280: revision B and newer • ATmega1281: revision B and newer • ATmega2560: revision F and newer • ATmega2561: revision F and newer Table 31-5. Symbol Characteristics of Enhanced Power-On Reset. TA= -40 to +85°C.
Table 31-7. 2-wire Serial Bus Requirements Symbol Parameter VIL VIH (1) Min. Max. Input Low-voltage -0.5 0.3 VCC Input High-voltage 0.7 VCC VCC + 0.5 Vhys Hysteresis of Schmitt Trigger Inputs (1) VOL Output Low-voltage tr (1) Condition 0.05 3mA sink current Output Fall Time from VIHmin to VILmax (1) tSP Spikes Suppressed by Input Filter Ii Input Current each I/O Pin Ci(1) Capacitance for each I/O Pin Rp 20 + 0.1Cb(3)(2) 300 20 + 0.
6. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz. 7. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308kHz when fCK = 8MHz.
Figure 31-7. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 8 7 MOSI (Data Output) MSB ... LSB Figure 31-8. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
31.8 ADC Characteristics – Preliminary Data Table 31-9. Symbol ADC Characteristics, Singel Ended Channels Typ. (1) Max. (1) Condition Resolution Single Ended Conversion 10 Single Ended Conversion VREF = 4V, VCC = 4V, CLKADC= 200kHz 2.
Table 31-10. ADC Characteristics, Differential Channels Symbol Parameter Condition Gain = Resolution Absolute Accuracy(Including INL, DNL, Quantization Error, Gain and Offset Error) Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset Error Clock Frequency Min. (1) Typ.
Table 31-10. ADC Characteristics, Differential Channels (Continued) Symbol Max. (1) Unit s 65 260 µs VCC - 0.3 VCC + 0.3 2.7 AVCC - 0.5 GND VCC Input Differential Voltage -VREF/Gain VREF/Gain ADC Conversion Output -511 511 Parameter Condition Min. (1) Conversion Time AVCC Analog Supply Voltage VREF Reference Voltage Typ.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. Table 31-12. External Data Memory Characteristics, 4.5 to 5.5 Volts, 1 Cycle Wait-state 8MHz Oscillator Min. Max. Variable Oscillator Symbol Parameter Min. Max. Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 240 2.0tCLCL-10 15 tDVWH Data Valid to WR High 240 2.0tCLCL 16 tWLWH WR Pulse Width 240 2.
Table 31-15. External Data Memory Characteristics, 2.7 to 5.5 Volts, No Wait-state 4MHz Oscillator Min. Max. Variable Oscillator Symbol Parameter Min. Max. Unit 0 1/tCLCL Oscillator Frequency 0.0 8 MHz 1 tLHLL ALE Pulse Width 235 tCLCL-15 2 tAVLL Address Valid A to ALE Low 115 0.5tCLCL-10(1) 3a tLLAX_ST Address Hold After ALE Low, write access 5 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 5 4 tAVLLC Address Valid C to ALE Low 115 0.
Table 31-17. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 1, SRWn0 = 0 4MHz Oscillator Min. Variable Oscillator Symbol Parameter Max. Min. Max. Unit 0 1/tCLCL Oscillator Frequency 0.0 8 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 735 3.0tCLCL-15 15 tDVWH Data Valid to WR High 750 3.0tCLCL 16 tWLWH WR Pulse Width 735 3.0tCLCL-15 690 3.0tCLCL-60 ns Table 31-18. External Data Memory Characteristics, 2.7 to 5.
Figure 31-10. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 3a DA7:0 Prev. data Address 13 Data XX 14 16 6 Write 2 WR 3b DA7:0 (XMBK = 0) 11 9 Data 5 Read Address 10 8 12 RD Figure 31-11. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T4 T5 T6 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 DA7:0 Prev.
Figure 31-12. External Memory Timing (SRWn1 = 1, SRWn0 = 1)() T1 T2 T3 T4 T6 T5 T7 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 3a DA7:0 Prev. data Address 13 XX Data 14 16 6 Write 2 WR 9 3b Address 11 Data 5 Read DA7:0 (XMBK = 0) 10 8 12 RD The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external).
32. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off.
Figure 32-2. Active Supply Current vs. Frequency (1MHz - 16MHz) 25 5.5V 5.0V 20 ICC (m A) 4.5V 15 4.0V 10 3.3V 2.7V 5 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 32-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 14 85°C 25°C -40°C 12 ICC (mA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 2.5 -40°C 85°C 25°C 2 ICC (mA) 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.7 0.6 -40°C ICC (mA) 0.5 0.4 25°C 85°C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 32-6. Idle Supply Current vs. Low Frequency (0.1MHz - 1.0MHz) 0.6 5.5V 0.5 5.0V ICC (mA) 0.4 4.5V 4.0V 0.3 3.3V 0.2 2.7V 1.8V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 32-7. Idle Supply Current vs. Frequency (1MHz - 16MHz) 8 7 5.5V 6 5.0V 5 ICC (m A) 32.2 4.5V 4 4.0V 3 2 3.3V 2.7V 1 1.
Figure 32-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 3.5 85°C 25°C -40°C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.9 -40°C 0.8 0.7 85°C 25°C ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)I 0.3 -40°C 0.25 ICC (m A) 0.2 0.15 25°C 85°C 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 32.2.1 Supply Current of IO modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
Table 32-2. Additional Current Consumption (percentage) in Active and Idle mode Additional Current consumption compared to Active with external clock Additional Current consumption compared to Idle with external clock PRUSART3 3.0% 17% PRUSART2 3.0% 17% PRUSART1 3.0% 17% PRUSART0 3.0% 17% PRTWI 4.4% 24% PRTIM5 1.8% 10% PRTIM4 1.8% 10% PRTIM3 1.8% 10% PRTIM2 4.3% 23% PRTIM1 1.8% 10% PRTIM0 1.5% 8.0% PRSPI 3.3% 18% PRADC 4.
Power-down Supply Current Figure 32-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 4 85°C 3.5 3 ICC (µA) 2.5 2 1.5 -40°C 25°C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 12 85°C 10 -40°C 25°C 8 ICC (µA) 32.3 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Power-save Supply Current Figure 32-13. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 11 25°C 10 ICC(µA) 9 8 7 6 5 4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-14. Power-save Supply Current vs. VCC (Watchdog Timer Enabled) 9 8 25°C 7 6 I CC (µA) 32.4 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
32.5 Standby Supply Current Figure 32-15. Standby Supply Current vs. VCC (Watchdog Timer Disabled) 0.2 6MHz xtal 6MHz res 0.18 0.16 ICC (mA) 0.14 4MHz res 4MHz xtal 0.12 0.1 0.08 2MHz res 2MHz xtal 0.06 1MHz res 455kHz res 0.04 0.02 32kHz xtal 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 32-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 40 IOP (µA) 32.6 30 20 10 25°C 85°C -40°C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 32-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 90 80 70 IOP (µA) 60 50 40 30 20 85°C 25°C -40°C 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 32-18. I/O Pin Pull-up Resistor Current vs.
Figure 32-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (µA) 30 25 20 15 10 25°C -40°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) Figure 32-20. Reset pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 70 60 IRESET (µA) 50 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1 1.5 2 2.
Figure 32-21. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET (µA) 80 60 40 20 25°C -40°C 85°C 0 0 1 2 3 4 5 6 VRESET (V) Pin Driver Strength Figure 32-22. I/O Pin output Voltage vs.Sink Current (VCC = 3V) 1 0.9 85°C 0.8 VOL (V) 32.7 0.7 25°C 0.6 -40°C 0.5 0.4 0.3 0.2 0.
Figure 32-23. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 85°C 0.5 25°C -40°C VOL (V) 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (mA) Figure 32-24. I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.5 3 VOH (V) 2.5 -40°C 25°C 85°C 2 1.5 1 0.
Figure 32-25. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 0 5 10 15 20 25 IOH (mA) Pin Threshold and Hysteresis Figure 32-26. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as “1“) 3.5 -40°C 25°C 85°C 3 2.5 Threshold (V) 32.8 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-27. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as “0“) 2.5 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-28. I/O Pin Input Hysteresis 0.8 -40°C Input Hyst eresis (mV) 0.7 0.6 0.5 25°C 85°C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-29. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as “1“) 2.5 -40°C 25°C 85°C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-30. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as “0“) 2.5 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-31. Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 0.1 -40°C 25°C 85°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 60 80 100 VCC (V) BOD Threshold and Analog Comparator Offset Figure 32-32. BOD Threshold vs. Temperature (BOD Level is 4.3V) 4.4 4.35 Rising Vcc Threshold (V) 32.9 4.3 4.25 Falling Vcc 4.
Figure 32-33. BOD Threshold vs. Temperature (BOD Level is 2.7V) 2.8 Rising Vcc Threshold (V) 2.75 2.7 Falling Vcc 2.65 2.6 -60 -40 -20 0 20 40 60 80 60 80 100 Temperature (°C) Figure 32-34. BOD Threshold vs. Temperature (BOD Level is 1.8V) 1.9 1.85 T hre shold ( V ) Rising Vcc 1.8 Fallling Vcc 1.75 1.
32.10 Internal Oscillator Speed Figure 32-35. Watchdog Oscillator Frequency vs. VCC 128 126 -40°C FRC (kHz) 124 25°C 122 120 118 116 85°C 114 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-36. Watchdog Oscillator Frequency vs. Temperature 128 126 FRC (kHz) 124 122 120 2.1V 2.7V 3.3V 4.0V 5.
Figure 32-37. Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.3 85°C 8.2 FRC (MHz) 8.1 25°C 8 7.9 -40°C 7.8 7.7 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-38. Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.5 5.0V 8.4 3.0V FRC (MHz) 8.3 8.2 8.1 8 7.
Figure 32-39. Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 16 85°C 25°C -40°C 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 32.11 Current Consumption of Peripheral Units Figure 32-40. Brownout Detector Current vs. VCC 30 85°C 25°C -40°C 25 ICC (µA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-41. ADC Current vs. VCC (AREF = AVCC) 350 -40°C 25°C 85°C 300 ICC (µA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-42. AREF External Reference Current vs. VCC 250 -40°C 25°C 85°C 200 ICC (µA) 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-43. Watchdog Timer Current vs. VCC 9 -40°C 8 25°C 85°C 7 ICC (µA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-44. Analog Comparator Current vs. VCC 100 -40°C 25°C 85°C 90 80 ICC (µA) 70 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-45. Programming Current vs. VCC 16 -40°C 14 12 25°C ICC (mA) 10 8 85°C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 32.12 Current Consumption in Reset and Reset Pulsewidth Figure 32-46. Reset Supply Current vs VCC (0.1MHz - 1.0MHz, Excluding Current Through The Reset Pull-up) 0.35 5.5V 0.3 5.0V 0.25 ICC (m A) 4.5V 0.2 4.0V 0.15 3.3V 0.1 2.7V 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-47. Reset Supply Current vs. VCC (1MHz - 16MHz, Excluding Current Through The Reset Pull-up) 4 5.5V 3.5 5.0V ICC (m A) 3 4.5V 2.5 2 4.0V 1.5 1 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 32-48. Minimum Reset Pulse Width vs. VCC 2500 Pu lsewidth (ns) 2000 1500 1000 85°C 25°C -40°C 500 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
33. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x1FF) Reserved - - - - - - - - - - - - - - - - - - - ...
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x100) PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 page 99 (0xFF) Reserved - - - - - - - - (0xFE) Reserved - - - - - - - - (0xFD) Reserved - - - - - - - - (0xFC) Reserved - - - - - - - - (0xFB) Reserved - - - - - - - - (0xFA) Reserved - - - - - - - - (0xF9) Reserved - - - - - - - - (0xF8) Reserved - - - - - - - - (0xF7) Reserved -
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE page 261 (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE page 263 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 page 262 2-wire Serial Interface Data Register page 263 (0xB8) TWBR (0xB7) Reserved - - - 2-wire Serial Interface Bit Rate Register - - - - - page 261 (0xB6) ASSR - EXCLK AS2 TCN2UB OCR2AUB OC
Address Name (0x78) ADCL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x77) Reserved - - - - - - - (0x76) Reserved - - - - - - - - (0x75) XMCRB XMBK - - - - XMM2 XMM1 XMM0 (0x74) XMCRA SRE SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 page 36 (0x73) TIMSK5 - - ICIE5 - OCIE5C OCIE5B OCIE5A TOIE5 page 162 (0x72) TIMSK4 - - ICIE4 - OCIE4C OCIE4B OCIE4A TOIE4 page 161 (0x71) TIMSK3 - - ICIE3 - OCIE3C OCIE3B OCIE3A TOIE3 page 161 (
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x14 (0x34) PORTG - - PORTG5 PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 page 98 0x13 (0x33) DDRG - - DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 page 98 0x12 (0x32) PING - - PING5 PING4 PING3 PING2 PING1 PING0 page 98 0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 page 97 0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 page 98 0x0F (0x2F) PINF PINF7 PINF6 PINF
34.
Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), R
Mnemonics Operands Description Operation Flags #Clocks OUT P, Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A Note: EICALL and EIJMP do not exist in ATmega640/1280/1281.
35. Ordering Information 35.1 ATmega640 Speed [MHz](2) 8 16 Notes: Power Supply Ordering Code Package(1)(3) 1.8 - 5.5V ATmega640V-8AU ATmega640V-8AUR(4) ATmega640V-8CU ATmega640V-8CUR(4) 100A 100A 100C1 100C1 2.7 - 5.5V ATmega640-16AU ATmega640-16AUR(4) ATmega640-16CU ATmega640-16CUR(4) 100A 100A 100C1 100C1 Operation Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form.
35.2 ATmega1280 Speed [MHz](2) 8 16 Notes: Power Supply Ordering Code Package(1)(3) 1.8V - 5.5V ATmega1280V-8AU ATmega1280V-8AUR(4) ATmega1280V-8CU ATmega1280V-8CUR(4) 100A 100A 100C1 100C1 2.7V - 5.5V ATmega1280-16AU ATmega1280-16AUR(4) ATmega1280-16CU ATmega1280-16CUR(4) 100A 100A 100C1 100C1 Operation Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
35.3 ATmega1281 Speed [MHz](2) 8 16 Notes: Ordering Code Package(1)(3) 1.8 - 5.5V ATmega1281V-8AU ATmega1281V-8AUR(4) ATmega1281V-8MU ATmega1281V-8MUR(4) 64A 64A 64M2 64M2 2.7 - 5.5V ATmega1281-16AU ATmega1281-16AUR(4) ATmega1281-16MU ATmega1281-16MUR(4) 64A 64A 64M2 64M2 Power Supply Operation Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
35.4 ATmega2560 Speed [MHz](2) 8 16 Notes: Power Supply Ordering Code Package(1)(3) 1.8V - 5.5V ATmega2560V-8AU ATmega2560V-8AUR(4) ATmega2560V-8CU ATmega2560V-8CUR(4) 100A 100A 100C1 100C1 4.5V - 5.5V ATmega2560-16AU ATmega2560-16AUR(4) ATmega2560-16CU ATmega2560-16CUR(4) 100A 100A 100C1 100C1 Operation Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
35.5 ATmega2561 Speed [MHz](2) 8 16 Notes: Power Supply Ordering Code Package(1)(3) 1.8V - 5.5V ATmega2561V-8AU ATmega2561V-8AUR(4) ATmega2561V-8MU ATmega2561V-8MUR(4) 64A 64A 64M2 64M2 4.5V - 5.5V ATmega2561-16AU ATmega2561-16AUR(4) ATmega2561-16MU ATmega2561-16MUR(4) 64A 64A 64M2 64M2 Operation Range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form.Contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
36. Packaging Information 36.1 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM A – – 1.20 A1 0.05 – 0.15 SYMBOL Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. MAX A2 0.95 1.
36.2 100C1 0.12 Z E Marked A1 Identifier SIDE VIEW D A TOP VIEW A1 Øb e A1 Corner 0.90 TYP 10 9 8 7 6 5 4 3 2 1 A 0.90 TYP B C D COMMON DIMENSIONS (Unit of Measure = mm) E D1 F e SYMBOL MIN NOM MAX H A 1.10 – 1.20 I A1 0.30 0.35 0.40 D 8.90 9.00 9.10 E 8.90 9.00 9.10 G J E1 BOTTOM VIEW D1 7.10 7.20 7.30 E1 7.10 7.20 7.30 Øb 0.35 0.40 0.45 e NOTE 0.80 TYP 5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 100C1, 100-ball, 9 x 9 x 1.
36.3 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.
36.4 64M2 D Marked pin# 1 I D E C SEATING PLANE A1 TOP VIEW A3 A K 0.08 C L Pin #1 Corner D2 1 2 3 SIDE VIEW Pin #1 Triangle Option A COMMON DIMENSIONS (Unit of measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 K Option C b e Pin #1 Notch (0.20 R) BOTTOM VIEW 0.20 REF b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 7.50 7.65 7.80 E 8.90 9.00 9.10 E2 7.50 7.65 7.80 e Notes: 1.
37. Errata 37.1 ATmega640 rev. B • Inaccurate ADC conversion in differential mode with 200× gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None. 2.
Problem Fix/Workaround None. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 37.5 ATmega1281 rev. B • High current consumption in sleep mode 1.
37.10 ATmega2560 rev. C • High current consumption in sleep mode 1. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 37.11 ATmega2560 rev. B Not sampled. 37.12 ATmega2560 rev. A • • • • • • 1.
5. IN/OUT instructions may be executed twice when Stack is in external RAM If either an IN or an OUT instruction is executed directly before an interrupt occurs and the stack pointer is located in external ram, the instruction will be executed twice. In some cases this will cause a problem, for example: - If reading SREG it will appear that the I-flag is cleared. - If writing to the PIN registers, the port will toggle twice. - If reading registers with interrupt flags, the flags will appear to be cleared.
37.18 ATmega2561 rev. A • • • • • • 1. Non-Read-While-Write area of flash not functional Part does not work under 2.4 Volts Incorrect ADC reading in differential mode Internal ADC reference has too low value IN/OUT instructions may be executed twice when Stack is in external RAM EEPROM read from application code does not work in Lock Bit Mode 3 Non-Read-While-Write area of flash not functional The Non-Read-While-Write area of the flash is not working as expected.
- Use internal RAM for stack pointer. 6. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Workaround Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM.
38. Datasheet Revision History Note that the referring page numbers in this section are referring to this document. The referring revisions in this section are referring to the document revision. 38.1 Rev. 2549Q-02/2014 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 38.2 Rev. 2549P-10/2012 1. 2. 3. 38.3 Replaced drawing of “64M2” on page 415. Former page 439 has been deleted as the content of this page did not belong there (same page as the last page). Some small correction made in the setup. Rev.
5. 6. 7. 38.5 Rev. 2549M-09/2010 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 38.6 Updated typos in Figure 26-9 on page 276 and in Figure 26-10 on page 277. Note is added below Table 1-1 on page 3. The values for “typical characteristics” in Table 31-9 on page 365 and Table 31-10 on page 366, has been rounded. Units for tRST and tBOD in Table 31-3 on page 360 have been changed from “ns” to “µs”. The figure text for Table 31-2 on page 359 has been changed.
4. 5. 6: 7. 8. 9. 10. 38.8 Rev. 2549J-09/06 1. 2. 3. 4. 5. 6. 38.9 Updated “Bit 1 – EEPE: EEPROM Programming Enable” on page 35. Updated Assembly code example in “Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used.
5. 6. 7. 8. 9. 10. Updated note for Table 12-1 on page 65. Updated Figure 26-9 on page 276 and Figure 26-10 on page 277. Updated “Setting the Boot Loader Lock Bits by SPM” on page 316. Updated “Ordering Information” on page 407. Added Package information “100C1” on page 413. Updated “Errata” on page 416. 38.12 Rev. 2549F-04/06 1. 2. 3. 4. Updated Figure 9-3 on page 29, Figure 9-4 on page 30 and Figure 9-5 on page 30. Updated Table 20-2 on page 182 and Table 20-3 on page 182.
38.15 Rev. 2549C-09/05 1. 2. 3. 4. 5. 6. 7. 8. Updated Speed Grade in section “Features” on page 1. Added “Resources” on page 10. Updated “SPI – Serial Peripheral Interface” on page 190. In Slave mode, low and high period SPI clock must be larger than 2 CPU cycles. Updated “Bit Rate Generator Unit” on page 242. Updated “Maximum speed vs. VCC” on page 373. Updated “Ordering Information” on page 407. Updated “Packaging Information” on page 412. Package 64M1 replaced by 64M2. Updated “Errata” on page 416.
Table of Contents Features .................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 5 2.1Block Diagram ...........................................................................................................5 2.
10.3Clock Sources .......................................................................................................40 10.4Low Power Crystal Oscillator .................................................................................41 10.5Full Swing Crystal Oscillator ..................................................................................42 10.6Low Frequency Crystal Oscillator ..........................................................................43 10.
14.2Reset and Interrupt Vector placement .................................................................102 14.3Moving Interrupts Between Application and Boot Section ...................................107 14.4Register Description ............................................................................................108 15 External Interrupts ............................................................................... 109 15.1Pin Change Interrupt Timing ...........................................
19.2Description ...........................................................................................................167 20 8-bit Timer/Counter2 with PWM and Asynchronous Operation ....... 169 20.1Overview ..............................................................................................................169 20.2Timer/Counter Clock Sources .............................................................................170 20.3Counter Unit .......................................................
24.1Features ..............................................................................................................236 24.22-wire Serial Interface Bus Definition ..................................................................236 24.3Data Transfer and Frame Format ........................................................................237 24.4Multi-master Bus Systems, Arbitration, and Synchronization ..............................239 24.5Overview of the TWI Module .................................
28.4Boundary-scan Specific JTAG Instructions .........................................................297 28.5Boundary-scan Chain ..........................................................................................298 28.6Boundary-scan Related Register in I/O Memory .................................................301 28.7ATmega640/1280/1281/2560/2561 Boundary-scan Order ..................................301 28.8Boundary-scan Description Language Files .................................................
32.2Idle Supply Current ..............................................................................................376 32.3Power-down Supply Current ................................................................................380 32.4Power-save Supply Current .................................................................................381 32.5Standby Supply Current ......................................................................................382 32.6Pin Pull-up ............................
37.11ATmega2560 rev. B ...........................................................................................418 37.12ATmega2560 rev. A ...........................................................................................418 37.13ATmega2561 rev. F ...........................................................................................419 37.14ATmega2561 rev. E ...........................................................................................419 37.15ATmega2561 rev. D .................
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