Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
42
Figure 11-1. Reset Logic
11.3 Power-on Reset
A power-on reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in
Section 29.5 “System and Reset Characteristics” on page 272. The POR is activated whenever V
CC
is below the detection
level. The POR circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage.
A power-on reset (POR) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold
voltage invokes the delay counter, which determines how long the device is kept in RESET after V
CC
rise. The RESET signal
is activated again, without any delay, when V
CC
decreases below the detection level.
Figure 11-2. MCU Start-up, RESET
Tied to V
CC
Power-on Reset
Circuit
Brown-out
Reset Circuit
MCU Status
Register (MCUSR)
Reset Circuit
Pull-up Resistor
BODLEVEL [2..0]
S
Q
R
DATA BUS
CK
SUT[1:0]
CKSEL[3:0]
RSTDISBL
COUNTER RESET
INTERNAL RESET
TIMEOUT
SPIKE
FILTER
RESET
VCC
Delay Counters
Watchdog
Timer
Watchdog
Oscillator
Clock
Generator
PORF BORF
WDRF
EXTRF
V
CC
V
CCRR
RESET
INTERNAL
RESET
TIME-OUT
t
TOUT
V
PORMAX
V
PORMIN
V
RST