Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
278
Figure 29-7. Parallel Programming Timing, Loading Sequence with Timing Requirements
(1)
Note: 1. The timing requirements shown in Figure 29-6 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to loading operation.
Figure 29-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements
(1)
Note: 1. The timing requirements shown in Figure 29-6 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to reading operation.
XTAL1
BS1
PAGEL
DATA
XA0
XA1
t
XLXH
t
PLXH
t
XLPH
Load Address
(Low Byte)
Load Data
(Low Byte)
Load Data
(High Byte)
Load Address
(Low Byte)
Load Data
ADDR0 (Low Byte) ADDR1 (Low Byte)DATA (Low Byte) DATA (High Byte)
XTAL1
BS1
OE
DATA
XA0
XA1
t
BVDV
t
XLOL
t
OLDV
t
OHDZ
Load Address
(Low Byte)
Read Data
(Low Byte)
Read Data
(High Byte)
Load Address
(Low Byte)
ADDR0 (Low Byte) ADDR1 (Low Byte)DATA (Low Byte) DATA (High Byte)