Datasheet

273
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
29.6 SPI Timing Characteristics
See Figure 29-3 and Figure 29-4 for details.
Table 29-7. SPI Timing Parameters
No. Description Mode Min. Typ Max Unit
1 SCK period Master See Table 19-5
ns
2 SCK high/low Master 50% duty cycle
3 Rise/fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5  t
sck
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4  t
ck
11 SCK high/low
(1)
Slave 2  t
ck
12 Rise/fall time Slave 1600
13 Setup Slave 10
14 Hold Slave t
ck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Slave 20
Notes: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
CLCL
for f
CK
< 12MHz
- 3 t
CLCL
for f
CK
> 12MHz
2. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR
microcontrollers manufactured in the same process technology. These values are preliminary values repre-
senting design targets, and will be updated after characterization of actual silicon.