Datasheet

243
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
27.8.5 Consideration While Updating BLS
Special care must be taken if the user allows the Boot Loader section to be updated by leaving boot lock bit11
unprogrammed. An accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates
might be impossible. If it is not necessary to change the boot loader software itself, it is recommended to program the boot
lock bit11 to protect the boot loader software from any internal software changes.
27.8.6 Prevent Reading the RWW Section during Self-programming
During self-programming (either page erase or page write), the RWW section is always blocked for reading. The user
software itself must prevent that this section is addressed during the self programming operation. The RWWSB in the
SPMCSR will be set as long as the RWW section is busy. During self-programming the interrupt vector table should be
moved to the BLS as described in Section 11.8 “Watchdog Timer” on page 45, or the interrupts must be disabled. Before
addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the
RWWSRE. See Section 27.8.13 “Simple Assembly Code Example for a Boot Loader” on page 245 for an example.
27.8.7 Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock bits and general Lock Bits, write the desired data to R0, write “X0001001” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR.
See Table 27-2 and Table 27-3 for how the different settings of the boot loader bits affect the flash access.
If bits 5...0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM instruction is executed within
four cycles after BLBSET and SELFPRGEN are set in SPMCSR. The Z-pointer is don’t care during this operation, but for
future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the lO
ck
bits). For future
compatibility it is also recommended to set bits 7 and 6 in R0 to “1” when writing the Lock bits. When programming the lock
bits the entire flash can be read during the operation.
27.8.8 EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to flash. Reading the fuses and lock bits from
software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit
(EEPE) in the EECR register and verifies that the bit is cleared before writing to the SPMCSR register.
27.8.9 Reading the Fuse and Lock Bits from Software
It is possible to read both the fuse and lock bits from software. To read the lock bits, load the Z-pointer with 0x0001 and set
the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the
BLBSET and SELFPRGEN bits are set in SPMCSR, the value of the lock bits will be loaded in the destination register. The
BLBSET and SELFPRGEN bits will auto-clear upon completion of reading the lock bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SELFPRGEN are
cleared, LPM will work as described in the instruction set manual.
The algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. To read the fuse
low byte, load the Z-pointer with 0x0000 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM instruction
is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the fuse low
byte (FLB) will be loaded in the destination register as shown below. Refer to Table 28-5 on page 253 for a detailed
description and mapping of the fuse low byte.
Bit 76543210
R0 1 1 BLB12 BLB11 BLB02 BLB01 LB2 LB1
Bit 76543210
Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1
Bit 76543210
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0