Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
236
26.3 Register Description
26.3.1 SPMCSR – Store Program Memory Control and Status Register
The store program memory control and status register contains the control bits needed to control the program memory
operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the status register is set (one), the SPM ready interrupt will be enabled.
The SPM ready Interrupt will be executed as long as the SELFPRGEN bit in the SPMCSR register is cleared. The interrupt
will not be generated during EEPROM write or SPM.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting read-while-write. It will always read as zero in Atmel
®
ATmega48PA.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SELFPRGEN, the next LPM instruction within three clock cycles will read a
byte from the signature row into the destination register. see Section 27.8.10 “Reading the Signature Row from Software” on
page 244 for details. An SPM instruction within four cycles after SIGRD and SELFPRGEN are set will have no effect. This
operation is reserved for future use and should not be used.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
The functionality of this bit in Atmel ATmega48PA is a subset of the functionality in the Atmel ATmega48PA/88PA/168PA. If
the RWWSRE bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will
be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
The functionality of this bit in Atmel ATmega48PA is a subset of the functionality in the Atmel ATmega48PA/88PA/168PA.
An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR register, will read either the
lock bits or the fuse bits (depending on Z0 in the Z-pointer) into the destination register. See Section 26.2.2 “Reading the
Fuse and Lock Bits from Software” on page 233 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes page
write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in
R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire page write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes page
erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will
auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted
during the entire page write operation.
• Bit 0 – SELFPRGEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET,
PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SELFPRGEN
is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the
Z-pointer. The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an SPM instruction,
or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SELFPRGEN bit remains
high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in
the lower five bits will have no effect.
Bit 7 6 5 4 3 2 1 0
0x37 (0x57) SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SELFPRGEN SPMCSR
Read/Write R/W R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0