Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
218
Figure 24-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 24-7. ADC Timing Diagram, Free Running Conversion
Table 24-1. ADC Conversion Time
Condition
Sample and Hold
(Cycles from Start of Conversion)
Conversion Time
(Cycles)
First conversion 13.5 25
Normal conversions, single ended 1.5 13
Auto Triggered conversions 2 13.5
12345678910111213 12
Cycle Number
One Conversion
Sign and MSB of Result
LSB of Result
Next Conversion
MUX and REFS
Update
Prescaler
Reset
Prescale
r
Reset
Conversion
Complete
ADC Clock
Trigger
Source
ADIF
ADATE
ADCH
ADCL
Sample and Hold
11 12 13 1 2 3 4
Cycle Number
One Conversion
Sign and MSB of Result
LSB of Result
Next Conversion
MUX and REFS
Update
Conversion
Complete
ADC Clock
ADSC
ADIF
ADCH
ADCL
Sample and Hold