Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
206
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Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying
to output a one on SDA while another master outputs a zero will lose the arbitration. Masters losing arbitration in SLA
will switch to slave mode to check if they are being addressed by the winning master. If addressed, they will switch to
SR or ST mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they will switch to
not addressed slave mode or wait until the bus is free and transmit a new START condition, depending on application
software action.
This is summarized in Figure 22-21. Possible status values are given in circles.
Figure 22-21. Possible Status Codes Caused by Arbitration
22.9 Register Description
22.9.1 TWBR – TWI Bit Rate Register
• Bits 7...0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the
SCL clock frequency in the master modes. See Section 22.5.2 “Bit Rate Generator Unit” on page 187 for calculating bit
rates.
22.9.2 TWCR – TWI Control Register
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by applying a
START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the
bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted
written to TWDR while the register is inaccessible.
Own
Address/ General Call
received
Direction
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
START SLA
NO
YES
Write
Read
38
68/78
Arbitration lost in SLA Arbitration lost in DATA
DATA STOP
B0
Bit 76543210
(0xB8) TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0xBC) TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE TWCR
Read/Write R/W R/W R/W R/W R R/W R R/W
Initial Value00000000