Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
154
Figure 20-2 shows a block diagram of the clock generation logic.
Figure 20-2. Clock Generation Logic, Block Diagram
Signal description:
txclk Transmitter clock (internal signal).
rxclk Receiver base clock (internal signal).
xcki Input from XCK pin (internal signal). Used for synchronous slave operation.
xcko Clock output to XCK pin (internal signal). Used for synchronous master operation.
fosc XTAL pin frequency (system clock).
20.3.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in
this section refers to Figure 20-2.
The USART baud rate register (UBRRn) and the down-counter connected to it function as a programmable prescaler or
baud rate generator. The down-counter, running at system clock (f
osc
), is loaded with the UBRRn value each time the
counter has counted down to zero or when the UBRRnL register is written. A clock is generated each time the counter
reaches zero. This clock is the baud rate generator clock output (= f
osc
/(UBRRn+1)). The transmitter divides the baud rate
generator clock output by 2, 8 or 16 depending on mode. The baud rate generator output is used directly by the receiver’s
clock and data recovery units. However, the recovery units use a state machine that uses 2, 8 or 16 states depending on
mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits.
Sync
Register
Edge
Detector
Prescaling
Down-Counter
/2
XCKn
Pin
/4
0
0
1
1
0
1
0
1
/2
UBRRn
DDR_XCKn UCPOLn
U2Xn
DDR_XCKn
UBRRn+1
txclk
rxclk
UMSELn
foscn
OSC
xcki
xcko