Datasheet
151
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
19.5.2 SPSR – SPI Status Register
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts
are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by
first reading the SPI status register with SPIF set, then accessing the SPI data register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are
cleared by first reading the SPI status register with WCOL set, and then accessing the SPI data register.
• Bit 5...1 – Reserved
These bits are reserved bits in the Atmel
®
ATmega48PA/88PA/168PA and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table
19-5). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as slave, the SPI
is only guaranteed to work at f
osc
/4 or lower.
The SPI interface on the Atmel ATmega48PA/88PA/168PA is also used for program memory and EEPROM downloading or
uploading. See 264 for serial programming and verification.
19.5.3 SPDR – SPI Data Register
The SPI data register is a read/write register used for data transfer between the register file and the SPI shift register. Writing
to the register initiates data transmission. Reading the register causes the shift register receive buffer to be read.
Table 19-5. Relationship Between SCK and the Oscillator Frequency
SPI2X SPR1 SPR0 SCK Frequency
0 0 0 f
osc
/4
0 0 1 f
osc
/16
0 1 0 f
osc
/64
0 1 1 f
osc
/128
1 0 0 f
osc
/2
1 0 1 f
osc
/8
1 1 0 f
osc
/32
1 1 1 f
osc
/64
Bit 76543210
0x2D (0x4D) SPIFWCOL–––––SPI2XSPSR
Read/Write RRRRRRRR/W
Initial Value00000000
Bit 76543210
0x2E (0x4E) MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value X X X X X X X X Undefined