Datasheet

137
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
18.11 Register Description
18.11.1 TCCR2A – Timer/Counter Control Register A
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
These bits control the output compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output
overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR)
bit corresponding to the OC2A pin must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. Table 18-2
shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM).
Table 18-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode.
Bit 7 6 5 4 3210
(0xB0) COM2A1 COM2A0 COM2B1 COM2B0 ––WGM21 WGM20 TCCR2A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 18-2. Compare Output Mode, non-PWM Mode
COM2A1 COM2A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 Toggle OC2A on compare match
1 0 Clear OC2A on compare match
1 1 Set OC2A on compare match
Table 18-3. Compare Output Mode, Fast PWM Mode
(1)
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
0 1
WGM22 = 0: Normal port operation, OC0A disconnected.
WGM22 = 1: Toggle OC2A on compare match.
1 0
Clear OC2A on compare match, set OC2A at BOTTOM,
(non-inverting mode).
1 1
Set OC2A on compare match, clear OC2A at BOTTOM,
(inverting mode).
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is
ignored, but the set or clear is done at BOTTOM. See Section 18.7.3 “Fast PWM Mode” on page 131 for more
details.