Datasheet

127
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
18.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 shows a block diagram
of the counter and its surrounding environment.
Figure 18-2. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or decrement TCNT2 by 1.
direction Selects between increment and decrement.
clear Clear TCNT2 (set all bits to zero).
clk
Tn
Timer/Counter clock, referred to as clk
T2
in the following.
top Signalizes that TCNT2 has reached maximum value.
bottom Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk
T2
).
clk
T2
can be generated from an external or internal clock source, selected by the clock select bits (CS22:0). When no clock
source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clk
T2
is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter control
register (TCCR2A) and the WGM22 located in the Timer/Counter control register B (TCCR2B). There are close connections
between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OC2A and
OC2B. For more details about advanced counting sequences and waveform generation, see
Section 18.7 “Modes of Operation” on page 130.
The Timer/Counter overflow flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can
be used for generating a CPU interrupt.
topbottom
TOVn
(Int. Req.)
DATA BUS
Control LogicTCNTn
clk
Tn
clear
count
direction
clk
I/O
Prescaler
T/C
Oscillator
TOSC1
TOSC2