Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
126
18.2.1 Registers
The Timer/Counter (TCNT2) and output compare register (OCR2A and OCR2B) are 8-bit registers. Interrupt request
(shorten as Int.Req.) signals are all visible in the timer interrupt flag register (TIFR2). All interrupts are individually masked
with the timer interrupt mask register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as
detailed later in this section. The asynchronous operation is controlled by the asynchronous status register (ASSR). The
clock select logic block controls which clock source he Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer
clock (clk
T2
).
The double buffered output compare register (OCR2A and OCR2B) are compared with the Timer/Counter value at all times.
The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the
output compare pins (OC2A and OC2B). See Section 18.5 “Output Compare Unit” on page 128 for details. The compare
match event will also set the compare flag (OCF2A or OCF2B) which can be used to generate an output compare interrupt
request.
18.2.2 Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter
number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used, i.e.,
TCNT2 for accessing Timer/Counter2 counter value and so on.
The definitions in Table 18-1 are also used extensively throughout the section.
18.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source
clk
T2
is by default equal to the MCU clock, clk
I/O
. When the AS2 bit in the ASSR register is written to logic one, the clock
source is taken from the Timer/Counter oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation,
see Section 18.11.8 “ASSR – Asynchronous Status Register” on page 142. For details on clock sources and prescaler, see
Section 18.10 “Timer/Counter Prescaler” on page 136.
Table 18-1. Definitions
Parameter Definition
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The
TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A register.
The assignment is dependent on the mode of operation.