Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
124
Figure 17-2. Prescaler for Timer/Counter0 and Timer/Counter1
(1)
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 17-1.
17.4 Register Description
17.4.1 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter synchronization mode. In this mode, the value that is written to the
PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that
the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them
advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by
hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by
hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset
of this prescaler will affect both timers.
Timer/Counter 1Clock Source
clk
T1
clk
I/O
PSRSYNC
T0
10-bit T/C Prescaler
0
CS10
CK/8
CK/64
CK/256
CK/1024
CS11
CS12
Synchronization
Clear
T1 Synchronization
Timer/Counter 0 Clock Source
clk
T0
0
CS00
CS01
CS02
Bit 765432 1 0
0x23 (0x43) TSM
– – – – – PSRASY PSRSYNC GTCCR
Read/Write R/W R RRRRR/WR/W
Initial Value000000 0 0