Datasheet

93
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than
f
clk_I/O
/2.5.
An external clock source can not be prescaled.
Figure 12-2. Prescaler for Synchronous Timer/Counters
Note: T3 input is not available on the
ATmega16U4/ATmega32U4 products. “Tn” only refers to either T0 or T1
inputs.
12.4 Register Description
12.4.1 General Timer/Counter Control Register – GTCCR
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is
written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals
asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same
value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the
PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters
When this bit is one, Timer/Counter0 and Timer/Counter1 and Timer/Counter3 prescaler will be Reset. This bit
is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0,
Timer/Counter1 and Timer/Counter3 share the same prescaler and a reset of this prescaler will affect all timers.
PSR10
Clear
Tn
Tn
clk
I/O
Synchronization
Synchronization
TIMER/COUNTERn CLOCK SOURCE
clk
Tn
TIMER/COUNTERn CLOCK SOURCE
clk
Tn
CSn0
CSn1
CSn2
CSn0
CSn1
CSn2
Bit 7 6 5 4 3 2 1 0
TSM – – – – – PSRASY PSRSYNC GTCCR
Read/Write R/W R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0