Datasheet

92
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
12. Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers
Timer/Counter0, 1, and 3 share the same prescaler module, but the Timer/Counters can have different
prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1,
or 3.
12.1 Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the
fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f
CLK_I/O
).
Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a fre-
quency of either f
CLK_I/O
/8, f
CLK_I/O
/64, f
CLK_I/O
/256, or f
CLK_I/O
/1024.
12.2 Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/Counter, and it
is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counter’s clock select, the
state of the prescaler will have implications for situations where a prescaled clock is used. One example of pres-
caling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of
system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However,
care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler
reset will affect the prescaler period for all Timer/Counters it is connected to.
12.3 External Clock Source
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn
). The Tn pin is sam-
pled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then
passed through the edge detector. Figure 12-1 shows a functional equivalent block diagram of the Tn synchro-
nization and edge detector logic. The registers are clocked at the positive edge of the internal system clock
(
clk
I/O
). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clk
Tn
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it
detects.
Figure 12-1. Tn/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge
has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock
cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct
sampling. The external clock must be guaranteed to have less than half the system clock frequency (f
ExtClk
<
f
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an
external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to varia-
tion of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and
Tn_sync
(To Clock
Select Logic)
Edge DetectorSynchronization
DQDQ
LE
DQ
Tn
clk
I/O