Datasheet

91
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
11.1.5 Pin Change Interrupt Control Register - PCICR
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is
enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually
by the PCMSK0 Register.
11.1.6 Pin Change Interrupt Flag Register – PCIFR
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in
SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical
one to it.
11.1.7 Pin Change Mask Register 0 – PCMSK0
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0
is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If
PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.
Bit 76543210
– – – – –PCIE0PCICR
Read/WriteRRRRRRRR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
– – – – –PCIF0PCIFR
Read/WriteRRRRRRRR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Val-
ue
00000000