Datasheet

90
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not
guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency
if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of
the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an
interrupt request as long as the pin is held low.
Note: 1. When changing the ISC61/ISC60 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the
EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
• Bit 3..0 – Reserved Bits
These bits are reserved bits and always read as zero.
11.1.3 External Interrupt Mask Register – EIMSK
• Bits 7..0 – INT6, INT3 – INT0: External Interrupt Request 6, 3 - 0 Enable
When an INT[6;3:0] bit is written to one and the I-bit in the Status Register (SREG) is set (one), the
corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control
Registers – EICRA and EICRB – defines whether the external interrupt is activated on rising or falling edge or
level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output.
This provides a way of generating a software interrupt.
11.1.4 External Interrupt Flag Register – EIFR
• Bits 7..0 – INTF6, INTF3 - INTF0: External Interrupt Flags 6, 3 - 0
When an edge or logic change on the INT[6;3:0] pin triggers an interrupt request, INTF7:0 becomes set (one). If
the I-bit in SREG and the corresponding interrupt enable bit, INT[6;3:0] in EIMSK, are set (one), the MCU will
jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can
be cleared by writing a logical one to it. These flags are always cleared when INT[6;3:0] are configured as level
interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these
pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See
“Digital Input Enable and Sleep Modes” on page 71 for more information.
ISC61 ISC60 Description
0 0 The low level of INT6 generates an interrupt request.
0 1 Any logical change on INT6 generates an interrupt request
1 0 The falling edge between two samples of INT6 generates an interrupt request.
1 1 The rising edge between two samples of INT6 generates an interrupt request.
Bit 76543210
- INT6 - - INT3 INT2 INT1 IINT0 EIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
- INTF6 - - INTF3 INTF2 INTF1 IINTF0 EIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0