Datasheet

89
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
11.1 Register Description
11.1.1 External Interrupt Control Register A – EICRA
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding
interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are
defined in the below table. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider
than the minimum pulse width given in the below table will generate an interrupt. Shorter pulses are not
guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the
completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt
will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can
occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK
Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a
logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled.
Note: 1. n = 3, 2, 1, or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the
EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
11.1.2 External Interrupt Control Register B – EICRB
• Bit 7..6 – Reserved Bits
These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.
• Bits 5, 4 – ISC61, ISC60: External Interrupt 6 Sense Control Bits
The External Interrupt 6 is activated by the external pin INT6 if the SREG I-flag and the corresponding interrupt
mask in the EIMSK is set. The level and edges on the external pin that activate the interrupt are defined in the
following table. The value on the INT6 pin are sampled before detecting edges. If edge or toggle interrupt is
Bit 76543210
ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
ISCn1 ISCn0 Description
0 0 The low level of INTn generates an interrupt request.
0 1 Any edge of INTn generates asynchronously an interrupt request.
1 0 The falling edge of INTn generates asynchronously an interrupt request.
1 1 The rising edge of INTn generates asynchronously an interrupt request.
Symbol Parameter Condition Min. Typ. Max. Units
t
INT
Minimum pulse width for asynchronous
external interrupt
50 ns
Bit 76543210
--ISC61ISC60----EICRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000