Datasheet

88
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
11. External Interrupts
The External Interrupts are triggered by the INT6, INT3:0 pin or any of the PCINT7..0 pins. Observe that, if
enabled, the interrupts will trigger even if the INT[6;3:0] or PCINT7..0 pins are configured as outputs. This
feature provides a way of generating a software interrupt.
The Pin change interrupt PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK0 Register control which
pins contribute to the pin change interrupts. Pin change interrupts on PCINT7 ..0 are detected asynchronously.
This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in
the specification for the External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT6). When the
external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is
held low. Note that recognition of falling or rising edge interrupts on INT6 requires the presence of an I/O clock,
described in “System Clock and Clock Options” on page 27. Low level interrupts and the edge interrupt on
INT3:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also
from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end
of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined
by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 27.