Datasheet

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR

Switching between input with pull-up and output low generates the same problem. The user must use either the

tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 10-1 summarizes the control signals for the pin value

10.2.4 Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit.

As shown in Figure 10-2 on page 68, the PINxn Register bit and the preceding latch constitute a synchronizer.

This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it

also introduces a delay. Figure 10-3 on page 69 shows a timing diagram of the synchronization when reading an

externally applied pin value. The maximum and minimum propagation delays are denoted t

pd,max

and t

pd,min

respectively.

Figure 10-3. Synchronization when Reading an Externally Applied Pin Value

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when

the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC

LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn

signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of

assertion.

Table 10-1. Port Pin Configurations

DDxn PORTxn

PUD

(in MCUCR) I/O Pull-up Comment

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled low

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)

XXX in r17, PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

pd, min