Datasheet

55
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference
is turned off before entering Power-down mode.
8.9 Watchdog Timer
ATmega16U4/ATmega32U4 has an Enhanced Watchdog Timer (WDT). The main features are:
•
Clocked from separate On-chip Oscillator
• Three Operating modes
– Interrupt
– System Reset
– Interrupt and System Reset
• Selectable Time-out period from 16ms to 8s
• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
Figure 8-8. Watchdog Timer
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives
an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is
required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the
time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the
device from sleep-modes, and also as a general system timer. One example is to limit the maximum time
allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System
Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in
Table 8-3. Internal Voltage Reference Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
V
BG
Bandgap reference voltage
V
CC
=2.7
T
A
=25°C
1.0 1.1 1.2 V
t
BG
Bandgap reference start-up time
V
CC
=2.7
T
A
=25°C
40 70 µs
I
BG
Bandgap reference current consumption
V
CC
=2.7
T
A
=25°C
10 µA
128kHz
OSCILLATOR
OSC/2K OSC/4K OSC/8K
OSC/16K OSC/32K OSC/64K
OSC/128K OSC/256K
OSC/512K
OSC/1024K
WDP0
WDP1
WDP2
WDP3
WATCHDOG
RESET
WDE
WDIF
WDIE
MCU RESET
INTERRUPT