Datasheet

43
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
7. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR
provides various sleep modes allowing the user to tailor the power consumption to the application’s
requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction
must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC
Noise Reduction, Power-down, Power-save, or Standby) will be activated by the SLEEP instruction.
See Table 7-1 on page 44 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the
instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes
up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
Figure 6-1 on page 27 presents the different clock systems in the ATmega16U4/ATmega32U4, and their
distribution. The figure is helpful in selecting an appropriate sleep mode.
7.1 Idle Mode
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the
CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters,
Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk
CPU
and clk
FLASH
,
while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer
Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not
required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator
Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a
conversion starts automatically when this mode is entered.
7.2 ADC Noise Reduction Mode
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction
mode, stopping the CPU but allowing the ADC, the external interrupts, 2-wire Serial Interface address match
and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and
clkFLASH, while allowing the other clocks to run (including clkUSB).
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is
enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion
Complete interrupt, only an External Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out
Reset, a 2-wire serial interface interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT6,
an external interrupt on INT3:0 or a pin change interrupt can wake up the MCU from ADC Noise Reduction
mode.
7.3 Power-down Mode
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In
this mode, the external Oscillator is stopped, while the external interrupts, the 2-wire Serial Interface, and the
Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, 2-
wire Serial Interface address match, an external level interrupt on INT6, an external interrupt on INT3:0, a pin
change interrupt or an asynchronous USB interrupt sources (VBUSTI, WAKEUPI), can wake up the MCU. This
sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.