Datasheet

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ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Figure 6-7. PLL Postcaler operation with division factor = 1.5
• Bit 3:0 – PDIV3:0 PLL Lock Frequency
These bits configure the PLL internal VCO clock reference according to the required output frequency value.
The optimal PLL configuration at 5V is: PLL output frequency = 96MHz, divided by 1.5 to generate the 64MHz
High Speed Timer clock, and divided by 2 to generate the 48MHz USB clock.
PDIV3 PDIV2 PDIV1 PDIV0 PLL Output Frequency
0 0 0 0 Not allowed
0 0 0 1 Not allowed
0 0 1 0 Not allowed
0 0 1 1 40MHz
0 1 0 0 48MHz
0 1 0 1 56MHz
0 1 1 0 Not allowed
0 1 1 1 72MHz
1 0 0 0 80MHz
1 0 0 1 88MHz
1 0 1 0 96MHz
1 0 1 1 Not allowed
1 1 0 0 Not allowed
1 1 0 1 Not allowed
1 1 1 0 Not allowed
1 1 1 1 Not allowed
Fi
Fi x ---
2
3