Datasheet

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ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started. Note that the Calibrated 8MHz Internal RC oscillator is automatically
enabled when the PLLE bit is set and with PINMUX (see PLLFRQ register) is set. The PLL must be disabled
before entering Power down mode in order to stop Internal RC Oscillator and avoid extra-consumption.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock. After the PLL is enabled, it takes about
several ms for the PLL to lock. To clear PLOCK, clear PLLE.
6.11.6 PLL Frequency Control Register – PLLFRQ
• Bit 7– PINMUX: PLL Input Multiplexer
This bit selects the clock input of the PLL:
 PINMUX = 0: the PLL input is connected to the PLL Prescaler, that has the Primary System Clock
as source
 PINMUX = 1: the PLL input is directly connected to the Internal Calibrated 8MHz RC Oscillator. This
mode allows to work in USB Low Speed mode with no crystal or using a crystal with a value
different of 8/16MHz.
• Bit 6– PLLUSB: PLL Postcaler for USB Peripheral
This bit select the division factor between the PLL output frequency and the USB module input frequency:
 PLLUSB = 0: no division, direct connection (if PLL Output = 48MHz)
 PLLUSB = 1: PLL Output frequency is divided by two and sent to USB module
(if PLL Output = 96MHz)
• Bit 5:4 – PLLTM1:0: PLL Postcaler for High Speed Timer
These bits codes for the division factor between the PLL Output Frequency and the High Speed Timer input
frequency.
Note that the division factor 1.5 will introduce some jitter in the clock, but keeping the error null since the aver-
age duty cycle is 50%. See Figures 6-7 for more details.
Bit 76543210
$32
PINMUX PLLUSB PLLTM1 PLLTM0 PDIV3 PDIV2 PDIV1 PDIV0 PLLFRQ
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000100
PLLTM1 PLLTM0 PLL Postcaler Factor for High-Speed Timer
0 0 0 (Disconnected)
0 1 1
1 0 1.5
1 1 2