Datasheet

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ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
6.11.5 PLL Control and Status Register – PLLCSR
• Bit 7:5 – Res: Reserved Bits
These bits are reserved and always read as zero.
• Bit 4 – PINDIV PLL Input Prescaler (1:1, 1:2)
These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the PLL from either a
8 or 16MHz input.
When using a 8MHz clock source, this bit must be set to 0 before enabling PLL (1:1).
When using a 16MHz clock source, this bit must be set to 1 before enabling PLL (1:2).
• Bit 3:2 – Res: Reserved Bits
These bits are reserved and always read as zero.
Table 6-10. Clock Prescaler Select
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
0 0 0 0 1
0 0 0 1 2
0 0 1 0 4
0 0 1 1 8
0 1 0 0 16
0 1 0 1 32
0 1 1 0 64
0 1 1 1 128
1 0 0 0 256
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Bit 76543210
$29 ($29)
PINDIV PLLE PLOCK PLLCSR
Read/Write R R R R/W R R R/W R
Initial Value 0 0 0 0 0 0 0 0