Datasheet

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ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are

directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one

single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

The device provides the following features: 16/32K bytes of In-System Programmable Flash with Read-While-

Write capabilities, 512Bytes/1K bytes EEPROM, 1.25/2.5K bytes SRAM, 26 general purpose I/O lines (CMOS

outputs and LVTTL inputs), 32 general purpose working registers, four flexible Timer/Counters with compare

modes and PWM, one more high-speed Timer/Counter with compare modes and PLL adjustable source, one

USART (including CTS/RTS flow control signals), a byte oriented 2-wire Serial Interface, a 12-channels 10-bit

ADC with optional differential input stage with programmable gain, an on-chip calibrated temperature sensor, a

programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG

test interface, also used for accessing the On-chip Debug system and programming and six software selectable

PROGRAM

COUNTER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMERS/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTE

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTE

DATA REGISTER

PORTD

INTERRUPT

UNIT

EEPROM

SPI

STATUS

SRAM

USART1

ALU

PORTB DRIVERS

PORTE DRIVERS

PORTF DRIVERS

PORTD DRIVERS

PORTC DRIVERS

PB7 - PB0

PE6

PF7 - PF4

RESET

VCC

GND

XTAL1

XTAL2

CONTROL

LINES

PC7

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

8-BIT DA TA BUS

USB 2.0

TIMING AND

CONTROL

OSCILLATOR

CALIB. OSC

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

ON-CHIP DEBUG

JTAG TAP

PROGRAMMING

LOGIC

BOUNDARY-

SCAN

DATA DIR.

REG. PORTF

DATA REGISTER

PORTF

POR - BOD

RESET

PD7 - PD0

TWO-WIRE SERIAL

INTERFACE

PLL

HIGH SPEED

TIMER/PWM

PE2

PC6PF1

PF0

ON-CHIP

USB PAD 3V

REGULATOR

UVcc

UCap

1uF

ANALOG

COMPARATOR

VBUS

ADC

AGND

AREF

AVCC

TEMPERATURE

SENSOR