Datasheet

368
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
28.8 Serial Programming Pin Mapping
Figure 28-10. Serial Programming and Verify
(1)
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.
2. V
CC
- 0.3V < AVCC < V
CC
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the
Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation
turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial
clock (SCK) input are defined as follows:
Low:> two CPU clock cycles for f
ck
< 12MHz, three CPU clock cycles for f
ck
>= 12MHz
High:> two CPU clock cycles for f
ck
< 12MHz, three CPU clock cycles for f
ck
>= 12MHz
28.8.1 Serial Programming Algorithm
When writing serial data to the device, data is clocked on the rising edge of SCK.
When reading data from the device, data is clocked on the falling edge of SCK. See Figure 28-11 on page 369
for timing details.
To program and verify the device in the serial programming mode, the following sequence is recommended (see
four byte instruction formats in
Table 28-16 on page 370):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some systems, the pro-
grammer can not guarantee that SCK is held low during power-up. In this case, RESET
must be given
a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial
instruction to pin PDI.
3. The serial programming instructions will not work if the communication is out of synchronization. When in
sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable
Table 28-14. Pin Mapping Serial Programming
Symbol Pins (TQFP-64) I/O Description
PDI PB2 I Serial Data in
PDO PB3 O Serial Data out
SCK PB1 I Serial Clock
VCC
GND
XTAL1
SCK
PDO
PDI
RESET
+1.8 - 5.5V
AVCC
+1.8 - 5.5V
(2)