Datasheet

36
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
6.9 PLL
The PLL is used to generate internal high frequency (up to 96MHz) clock for USB interface and/or High Speed
Timer module, the PLL input is supplied from an external low-frequency clock (the crystal oscillator or external
clock input pin from XTAL1).
6.9.1 Internal PLL
The internal PLL in the device generates a clock frequency between 32MHz and 96MHz from nominally 8MHz
input.
The source of the 8MHz PLL input clock is the output of the internal PLL clock prescaler that generates the
8MHz from the clock source multiplexer output (See “PLL Control and Status Register – PLLCSR” on page 40.
for PLL interface). The PLL prescaler allows a direct connection (8MHz oscillator) or a divide-by-2 stage for a
16MHz clock input.
The PLL output signal enters the PLL Postcaler stage before being distributed to the USB and High Speed
Timer modules. Each of these modules can choose an independent division ratio.
Figure 6-6. PLL Clocking System
6.10 Clock switch Algorithm
6.10.1 Switch from External Clock to RC Clock
if (Usb_suspend_detected()) // if (UDINT.SUSPI == 1)
{
Usb_ack_suspend(); // UDINT.SUSPI = 0;
Usb_freeze_clock(); // USBCON.FRZCLK = 1;
Disable_pll(); // PLLCSR.PLLE = 0;
Enable_RC_clock(); // CLKSEL0.RCE = 1;
while (!RC_clock_ready()); // while (CLKSTA.RCON != 1);
Select_RC_clock(); // CLKSEL0.CLKS = 0;
Disable_external_clock(); // CLKSEL0.EXTE = 0;
}
6.10.2 Switch from RC Clock to External Clock
if (Usb_wake_up_detected()) // if (UDINT.WAKEUPI == 1)
{
Usb_ack_wake_up(); // UDINT.WAKEUPI = 0;
Enable_external_clock(); // CKSEL0.EXTE = 1;
while (!External_clock_ready()); // while (CLKSTA.EXTON != 1);
8 MHz
RC OSCILLATOR
XTAL1
XTAL2
XTAL
OSCILLATOR
PLL
PLLE
Lock
Detector
clk
TMR
To System
Clock Prescaler
clk
8MHz
PLL clock
Prescaler
PINDIV
PDIV3..0
clk
USB
/2
/1.5
PLLTM1:0
PLLUSB
0
1
PINMUX
0
1
01
10
11
CKSEL3:0
PLOCK