Datasheet
317
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
24.9.3.2 ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers. If differential channels are
used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is
sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If
ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 309.
24.9.4 ADC Control and Status Register B – ADCSRB
• Bit 7 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. This mode enables higher conversion rate at the
expense of higher power consumption.
• Bit 5 – MUX5: Analog Channel Additional Selection Bits
This bit make part of MUX5:0 bits of ADRCSRB and ADMUX register, that select the combination of analog
inputs connected to the ADC (including differential amplifier configuration).
• Bit 3:0 – ADTS3:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC
conversion. If ADATE is cleared, the ADTS3:0 settings will have no effect. A conversion will be triggered by the
rising edge of the selected interrupt flag. Note that switching from a trigger source that is cleared to a trigger
source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a
conversion. Switching to Free Running mode (ADTS[3:0]=0) will not cause a trigger event, even if the ADC
Interrupt Flag is set.
Bit 151413121110 9 8
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
ADC1ADC0––––––ADCL
Bit 76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value00000000
00000000
Bit 76543210
ADHSM ACME MUX5 – ADTS3 ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R/W R/W R R R R/W R/W R/W
Initial Value00000000