Datasheet

307
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Figure 24-10. ADC Power Connections
Note: The same circuitry should be used for AVCC filtering on the ADC8-ADC13 side.
24.7.3 Offset Compensation Schemes
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as
much as possible. The remaining offset in the analog path can be measured directly by selecting the same
channel for both differential inputs. This offset residue can be then subtracted in software from the
measurement results. Using this kind of software based offset correction, offset on any channel can be reduced
below one LSB.
24.7.4 ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and V
REF
in 2
n
steps (LSBs). The lowest
code is read as 0, and the highest code is read as 2
n
-1.
Several parameters describe the deviation from the ideal behavior:
 Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB).
Ideal value: 0 LSB.
VCC
GND
100nF
Analog Ground Plane
(ADC0) PF0
(ADC7) PF7
(ADC1) PF1
(ADC4) PF4
(ADC5) PF5
(ADC6) PF6
AREF
GND
AVCC
34
35
36
37
38
39
40
41
42
43
44
1
10µH