Datasheet

303
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
then to “1”), only extended conversions are performed. The result from the extended conversions will be valid.
See “Prescaling and Conversion Timing” on page 300 for timing details.
The gain stage is optimized for a bandwidth of 4kHz at all gain settings. Higher frequencies may be subjected to
non-linear amplification. An external low-pass filter should be used if the input signal contains higher frequency
components than the gain stage bandwidth. Note that the ADC clock frequency is independent of the gain stage
bandwidth limitation. E.g. the ADC clock period may be 6µs, allowing a channel to be sampled at 12kSPS,
regardless of the bandwidth of this channel.
24.5 Changing Channel or Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which
the CPU has random access. This ensures that the channels and reference selection only takes place at a safe
point during the conversion. The channel and reference selection is continuously updated until a conversion is
started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient
sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion
completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after
ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until
one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be
taken when updating the ADMUX Register, in order to control which conversion will be affected by the new
settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is
changed in this period, the user cannot tell if the next conversion is based on the old or the new settings.
ADMUX can be safely updated in the following ways:
a. When ADATE or ADEN is cleared.
3. During conversion, minimum one ADC clock cycle after the trigger event.
4. After a conversion, before the interrupt flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
Special care should be taken when changing differential channels. Once a differential channel has been
selected, the stage may take as much as 125µs to stabilize to the new value. Thus conversions should not be
started within the first 125µs after selecting a new differential channel. Alternatively, conversion results obtained
within this period should be discarded.
The same settling time should be observed for the first differential conversion after changing ADC reference (by
changing the REFS1:0 bits in ADMUX).
The settling time and gain stage bandwidth is independent of the ADHSM bit setting.
24.5.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure that the correct
channel is selected:
 In Single Conversion mode, always select the channel before starting the conversion. The channel
selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method
is to wait for the conversion to complete before changing the channel selection.
 In Free Running mode, always select the channel before starting the first conversion. The channel
selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method
is to wait for the first conversion to complete, and then change the channel selection. Since the next
conversion has already started automatically, the next result will reflect the previous channel selection.
Subsequent conversions will reflect the new channel selection.