Datasheet

302
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Figure 24-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 24-7. ADC Timing Diagram, Free Running Conversion
24.4.1 Differential Channels
When using differential channels, certain aspects of the conversion need to be taken into consideration.
Differential conversions are synchronized to the internal clock CK
ADC2
equal to half the ADC clock frequency.
This synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs
at a specific phase of CK
ADC2
. A conversion initiated by the user (i.e., all single conversions, and the first free
running conversion) when CK
ADC2
is low will take the same amount of time as a single ended conversion (13
ADC clock cycles from the next prescaled clock cycle). A conversion initiated by the user when CK
ADC2
is high
will take 14 ADC clock cycles due to the synchronization mechanism. In Free Running mode, a new conversion
is initiated immediately after the previous conversion completes, and since CK
ADC2
is high at this time, all
automatically started (i.e., all but the first) Free Running conversions will take 14 ADC clock cycles.
If differential channels are used and conversions are started by Auto Triggering, the ADC must be switched off
between conversions. When Auto Triggering is used, the ADC prescaler is reset before the conversion is
started. Since the stage is dependent of a stable ADC clock prior to the conversion, this conversion will not be
valid. By disabling and then re-enabling the ADC between each conversion (writing ADEN in ADCSRA to “0”
Table 24-1. ADC Conversion Time
Condition First Conversion
Normal Conversion,
Single Ended
Auto Triggered
Conversion
Sample and Hold
(Cycles from Start of Convention)
14.5 1.5 2
Conversion Time
(Cycles)
25 13 13.5
1 2 3 4 5 6 7 8
9
10 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
34
Conversion
Complete
Sample & Hold
MUX and REFS
Update