Datasheet

300
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Figure 24-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing
conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the
ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In
this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF
is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can
also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion,
independently of how the conversion was started.
24.4 Prescaling and Conversion Timing
Figure 24-3. ADC Prescaler
By default, the successive approximation circuitry requires an input clock frequency between 50kHz and
200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the
ADC can be higher than 200kHz to get a higher sample rate. Alternatively, setting the ADHSM bit in ADCSRB
allows an increased ADC clock frequency at the expense of higher power consumption.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU
frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting
from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for
as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the
following rising edge of the ADC clock cycle. See “Differential Channels” on page 302 for details on differential
conversion timing.
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START
CLK
ADC
.
.
.
.
EDGE
DETECTOR
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2 CK/4 CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START