Datasheet

294
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
23.1 Register Description
23.1.1 ADC Control and Status Register B – ADCSRB
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer
is connected to the negative input to the Analog Comparator. When this bit is written logic zero, the Bandgap
reference is connected to the negative input of the Analog Comparator (See “Internal Voltage Reference” on
page 54.) For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 295.
23.1.2 Analog Comparator Control and Status Register – ACSR
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any
time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When
changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise an interrupt can occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator.
When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage
Reference” on page 54.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization
introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and
ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set.
ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is
cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt
is activated. When written logic zero, the interrupt is disabled.
Bit 7 6543210
ADHSM ACME MUX5 – ADTS3 ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R/W R/W R R R/W R/W R/W
Initial Value0 0000000
Bit 76543210
ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 N/A 0 0 0 0 0