Datasheet

290
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
• Bit 3 - RXSTPI - Received SETUP Interrupt Flag
Set by hardware to signal that the current bank contains a new valid SETUP packet. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
This bit is inactive (cleared) if the endpoint is an IN endpoint.
• Bit 2 - RXOUTI / KILLBK - Received OUT Data Interrupt Flag
Set by hardware to signal that the current bank contains a new packet. An interrupt (EPINTx) is triggered (if
enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
Kill Bank IN Bit
Set this bit to kill the last written bank.
Cleared by hardware when the bank is killed. Clearing by software has no effect.
See “Abort” on page 277 for more details on the Abort.
• Bit 1 - STALLEDI - STALLEDI Interrupt Flag
Set by hardware to signal that a STALL handshake has been sent, or that a CRC error has been detected in a
OUT isochronous endpoint.
Shall be cleared by software. Setting by software has no effect.
• Bit 0 - TXINI - Transmitter Ready Interrupt Flag
Set by hardware to signal that the current bank is free and can be filled. An interrupt (EPINTx) is triggered (if
enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
This bit is inactive (cleared) if the endpoint is an OUT endpoint.
• Bit 7 - FLERRE - Flow Error Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
• Bit 6 - NAKINE - NAK IN Interrupt Enable Bit
Set to enable an endpoint interrupt (EPINTx) when NAKINI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKINI is set.
• Bit 5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• Bit 4 - NAKOUTE - NAK OUT Interrupt Enable Bit
Set to enable an endpoint interrupt (EPINTx) when NAKOUTI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKOUTI is set.
Bit 7 6 5 4 3 2 1 0
FLERRE NAKINE - NAKOUTE RXSTPE RXOUTE STALLEDE TXINE UEIENX
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0