Datasheet

289
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
- 1 for IN endpoint
- 0 for OUT endpoint
Can not be set or cleared by software.
• Bits 1:0 - CURRBK1:0 - Current Bank (all endpoints except Control endpoint) Flag
Set by hardware to indicate the number of the current bank:
00bBank0
01bBank1
1xbReserved
Can not be set or cleared by software.
• Bit 7 - FIFOCON - FIFO Control Bit
For OUT and SETUP Endpoint:
Set by hardware when a new OUT message is stored in the current bank, at the same time than RXOUT or
RXSTP.
Clear to free the current bank and to switch to the following bank. Setting by software has no effect.
For IN Endpoint:
Set by hardware when the current bank is free, at the same time than TXIN.
Clear to send the FIFO data and to switch the bank. Setting by software has no effect.
• Bit 6 - NAKINI - NAK IN Received Interrupt Flag
Set by hardware when a NAK handshake has been sent in response of a IN request from the host. This triggers
an USB interrupt if NAKINE is sent.
Shall be cleared by software. Setting by software has no effect.
• Bit 5 - RWAL - Read/Write Allowed Flag
Set by hardware to signal:
- for an IN endpoint: the current bank is not full i.e. the firmware can push data into the FIFO
- for an OUT endpoint: the current bank is not empty, i.e. the firmware can read data from the FIFO
The bit is never set if STALLRQ is set, or in case of error.
Cleared by hardware otherwise.
This bit shall not be used for the control endpoint.
• Bit 4 - NAKOUTI - NAK OUT Received Interrupt Flag
Set by hardware when a NAK handshake has been sent in response of a OUT/PING request from the host. This
triggers an USB interrupt if NAKOUTE is sent.
Shall be cleared by software. Setting by software has no effect.
Bit 76543210
FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLEDI TXINI UEINTX
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0