Datasheet

286
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
• Bits 7:6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• Bit 5 - STALLRQ - STALL Request Handshake Bit
Set to request a STALL answer to the host for the next handshake.
Cleared by hardware when a new SETUP is received. Clearing by software has no effect.
See “STALL Request” on page 273 for more details.
• Bit 4 - STALLRQC - STALL Request Clear Handshake Bit
Set to disable the STALL handshake mechanism.
Cleared by hardware immediately after the set. Clearing by software has no effect.
See “STALL Request” on page 273 for more details.
• Bit 3 - RSTDT - Reset Data Toggle Bit
Set to automatically clear the data toggle sequence:
For OUT endpoint: the next received packet will have the data toggle 0.
For IN endpoint: the next packet to be sent will have the data toggle 0.
Cleared by hardware instantaneously. The firmware does not have to wait that the bit is cleared. Clearing by
software has no effect.
• 2 - Reserved
The value read from these bits is always 0. Do not set these bits.
• Bit 1 - Reserved
The value read from these bits is always 0. Do not set these bits.
• Bit 0 - EPEN - Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0 shall always be enabled after a
hardware or USB reset and participate in the device configuration.
Clear this bit to disable the endpoint. See “Endpoint Activation” on page 271 for more details.
• Bits 7:6 - EPTYPE1:0 - Endpoint Type Bits
Set this bit according to the endpoint configuration:
00b: Control10b: Bulk
01b: Isochronous11b: Interrupt
Bit 7 6 5 4 3 2 1 0
- - STALLRQ STALLRQC RSTDT - - EPEN UECONX
Read/Write R R W W W R R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
EPTYPE1:0 -----EPDIRUECFG0X
Read/Write R/W R/W R R R R R R/W
Initial Value00000000