Datasheet

278
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
Table 22-1. Abort Flow
22.15 Isochronous Mode
22.15.1 Underflow
An underflow can occur during IN stage if the host attempts to read a bank which is empty. In this situation, the
UNDERFI interrupt is triggered.
An underflow can also occur during OUT stage if the host send a packet while the banks are already full.
Typically, the CPU is not fast enough. The packet is lost.
It is not possible to have underflow error during OUT stage, in the CPU side, since the CPU should read only if
the bank is ready to give data (RXOUTI=1 or RWAL=1)
22.15.2 CRC Error
A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In this situation,
the STALLEDI interrupt is triggered. This does not prevent the RXOUTI interrupt from being triggered.
22.16 Overflow
In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if the host
attempts to write in a bank that is too small for the packet. In this situation, the OVERFI interrupt is triggered (if
enabled). The packet is acknowledged and the RXOUTI interrupt is also triggered (if enabled). The bank is filled
with the first bytes of the packet.
It is not possible to have overflow error during IN stage, in the CPU side, since the CPU should write only if the
bank is ready to access data (TXINI=1 or RWAL=1).
22.17 Interrupts
Figure 22-4 shows all the interrupts sources.
Endpoint
Abort
Abort done
Abort is based on the fact
that no banks are busy,
meaning that nothing has to
be sent.
Disable the TXINI interrupt.
Endpoint
reset
NBUSYBK
=0
Yes
Clear
UEIENX.
TXINE
No
KILLBK=1
KILLBK=1
Yes
Kill the last written
bank.
Wait for the end of the
procedure.
No