Datasheet

277
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can write data to the
bank, and cleared by hardware when the bank is full
.
22.14.1 Detailed Description
The data are written by the CPU, following the next flow:
 When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled (TXINE set) and TXINI is
set. The CPU can also poll TXINI or FIFOCON, depending the software architecture choice
 The CPU acknowledges the interrupt by clearing TXINI
 The CPU can write the data into the current bank (write in UEDATX)
 The CPU can free the bank by clearing FIFOCON when all the data are written, that is:
 after “N” write into UEDATX
 as soon as RWAL is cleared by hardware
If the endpoint uses two banks, the second one can be read by the HOST while the current is being written by
the CPU. Then, when the CPU clears FIFOCON, the next bank may be already ready (free) and TXINI is set
immediately.
22.14.1.1Abort
An “abort” stage can be produced by the host in some situations:
 In a control transaction: ZLP data OUT received during a IN stage
 In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN stage on the
IN endpoint
 ...
The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to perform the
following operations:
IN
DATA
(bank 0)
ACK
TXINI
FIFOCON
HW
Example with 1 IN data bank
write data from CPU
BANK 0
Example with 2 IN data banks
SW
SW SW
SW
IN
IN
DATA
(bank 0)
ACK
TXINI
FIFOCON
write data from CPU
BANK 0
SW
SW SW
SW
IN
DATA
(bank 1)
ACK
write data from CPU
BANK 0
write data from CPU
BANK 1
SW
HW
write data from CPU
BANK0
NAK