Datasheet

276
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can read data from the
bank, and cleared by hardware when the bank is empty.
22.13.2 Detailed description
22.13.2.1
The data are read by the CPU, following the next flow:
 When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled (RXOUTE set)
and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending on the software architecture
 The CPU acknowledges the interrupt by clearing RXOUTI
 The CPU can read the number of byte (N) in the current bank (N=BYCT)
 The CPU can read the data from the current bank (“N” read of UEDATX)
 The CPU can free the bank by clearing FIFOCON when all the data is read, that is:
 after “N” read of UEDATX
 as soon as RWAL is cleared by hardware
If the endpoint uses 2 banks, the second one can be filled by the HOST while the current one is being read by
the CPU. Then, when the CPU clear FIFOCON, the next bank may be already ready and RXOUTI is set
immediately.
22.14 IN endpoint management
IN packets are sent by the USB device controller, upon an IN request from the host. All the data can be written
by the CPU, which acknowledge or not the bank when it is full.Overview
The Endpoint must be configured first.
The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt if the TXINE bit
is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO and clears the FIFOCON bit to
allow the USB controller to send the data. If the IN Endpoint is composed of multiple banks, this also switches to
the next data bank. The TXINI and FIFOCON bits are automatically updated by hardware regarding the status
of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
OUT
DATA
(to bank 0)
ACK
RXOUTI
FIFOCON
HW
OUT
DATA
(to bank 0)
ACK
HW
SW
SW
SW
Example with 1 OUT data bank
read data from CPU
BANK 0
OUT
DATA
(to bank 0)
ACK
RXOUTI
FIFOCON
HW
OUT
DATA
(to bank 1)
ACK
SW
SW
Example with 2 OUT data banks
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 0
read data from CPU
BANK 1
NAK