Datasheet

275
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
22.12.2 Control Read
The next figure shows a control read transaction. The USB controller has to manage the simultaneous write
requests from the CPU and the USB host:
A NAK handshake is always generated at the first status stage command.
When the controller detect the status stage, all the data written by the CPU are erased, and clearing TXINI has
no effects.
The firmware checks if the transmission is complete or if the reception is complete.
The OUT retry is always ack’ed. This reception:
- set the RXOUTI flag (received OUT data)
- set the TXINI flag (data sent, ready to accept new data)
software algorithm:
set transmit ready
wait (transmit complete OR Receive complete)
if receive complete, clear flag and return
if transmit complete, continue
Once the OUT status stage has been received, the USB controller waits for a SETUP request. The SETUP
request have priority over any other request and has to be ACK’ed. This means that any other flag should be
cleared and the fifo reset when a SETUP is received.
WARNING: the byte counter is reset when the OUT Zero Length Packet is received. The firmware has to take
care of this.
22.13 OUT Endpoint Management
OUT packets are sent by the host. All the data can be read by the CPU, which acknowledges or not the bank
when it is empty.
22.13.1 Overview
The Endpoint must be configured first.
Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This triggers an interrupt if the
RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing the RXOUTI bit. The Firmware
read the data and clear the FIFOCON bit in order to free the current bank. If the OUT Endpoint is composed of
multiple banks, clearing the FIFOCON bit will switch to the next bank. The RXOUTI and FIFOCON bits are then
updated by hardware in accordance with the status of the new bank.
RXOUTI shall always be cleared before clearing FIFOCON.
SETUP
RXSTPI
RXOUTI
TXINI
USB line
HW SW
IN
HW SW
IN OUT OUT
NAK
SW
SW
HW
Wr Enable
HOST
Wr Enable
CPU
DATASETUP STATUS