Datasheet

272
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
A clear of EPEN acts as an endpoint reset (see “Endpoint Reset” on page 270 for more details). It also performs
the next operation:
 The configuration of the endpoint is kept (EPSIZE, EPBK, ALLOC kept)
 It resets the data toggle field
 The DPRAM memory associated to the endpoint is still reserved
See “Memory Management” on page 263 for more details about the memory allocation/reorganization.
22.7 Address Setup
The USB device address is set up according to the USB protocol:
 the USB device, after power-up, responds at address 0
 the host sends a SETUP command (SET_ADDRESS(addr))
 the firmware handles this request, and records that address in UADD, but keep ADDEN cleared
 the USB device firmware sends an IN command of 0 bytes (IN 0 Zero Length Packet)
 then, the firmware can enable the USB device address by setting ADDEN. The only accepted address by
the controller is the one stored in UADD.
ADDEN and UADD shall not be written at the same time.
UADD contains the default address 00h after a power-up or USB reset.
ADDEN is cleared by hardware:
 after a power-up reset
 when an USB reset is received
 or when the macro is disabled (USBE cleared)
When this bit is cleared, the default device address 00h is used.
22.8 Suspend, Wake-up and Resume
After a period of 3ms during which the USB line was inactive, the controller switches to the full-speed mode and
triggers (if enabled) the SUSPI (suspend) interrupt. The firmware may then set the FRZCLK bit.
The CPU can also, depending on software architecture, enter in the idle mode to lower again the power
consumption.
There are two ways to recover from the “Suspend” mode:
 First one is to clear the FRZCLK bit. This is possible if the CPU is not in the Idle mode.
 Second way, if the CPU is “idle”, is to enable the WAKEUPI interrupt (WAKEUPE set). Then, as soon as
an non-idle signal is seen by the controller, the WAKEUPI interrupt is triggered. The firmware shall then
clear the FRZCLK bit to restart the transfer.
There are no relationship between the SUSPI interrupt and the WAKEUPI interrupt: the WAKEUPI interrupt is
triggered as soon as there are non-idle patterns on the data lines. Thus, the WAKEUPI interrupt can occurs
even if the controller is not in the “suspend” mode.
When the WAKEUPI interrupt is triggered, if the SUSPI interrupt bit was already set, it is cleared by hardware.
When the SUSPI interrupt is triggered, if the WAKEUPI interrupt bit was already set, it is cleared by hardware.
22.9 Detach
The reset value of the DETACH bit is 1.
It is possible to re-enumerate a device, simply by setting and clearing the DETACH bit (but firmware must take
in account a debouncing delay of some milliseconds).