Datasheet

271
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as an answer to the
CLEAR_FEATURE USB command.
22.4 USB Reset
When an USB reset is detected on the USB line (SE0 state with a minimum duration of 2.5µs), the next
operations are performed by the controller:
 all the endpoints are disabled
 the default control endpoint remains configured (see “Endpoint Reset” on page 270 for more details)
If the CPU hardware reset function is activated (RSTCPU bit set in UDCON register), a reset is generated to the
CPU core without disabling the USB controller (that follows the same behavior than after a standard USB End of
Reset, and remains attached). That feature may be used to enhance device reliability.
22.5 Endpoint Selection
Prior to any operation performed by the CPU, the endpoint must first be selected. This is done by setting the
EPNUM2:0 bits (UENUM register) with the endpoint number which will be managed by the CPU.
The CPU can then access to the various endpoint registers and data.
22.6 Endpoint Activation
The endpoint is maintained under reset as long as the EPEN bit is not set.
The following flow must be respected in order to activate an endpoint:
Figure 22-2. Endpoint Activation Flow:
As long as the endpoint is not correctly configured (CFGOK cleared), the hardware does not acknowledge the
packets sent by the host.
CFGOK is will not be sent if the Endpoint size parameter is bigger than the DPRAM size.
Endpoint
Activation
CFGOK=1
ERROR
No
Yes
Endpoint activated
Activate the endpoint
Select the endpoint
EPEN=1
UENUM
EPNUM=x
Test the correct endpoint
configuration
UECFG1X
ALLOC
EPSIZE
EPBK
Configure:
- the endpoint size
- the bank parametrization
Allocation and reorganization of
the memory is made on-the-fly
UECFG0X
EPDIR
EPTYPE
...
Configure:
- the endpoint direction
- the endpoint type