Datasheet

27
ATmega16U4/32U4 [DATASHEET]
Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016
6. System Clock and Clock Options
6.1 Clock Systems and their Distribution
Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be
active at a given time. In order to reduce power consumption, the clocks to modules not being used can be
halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 43. The
clock systems are detailed below.
Figure 6-1. Clock Distribution
6.1.1 CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such
modules are the General Purpose Register File, the Status Register and the data memory holding the Stack
Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.
6.1.2 I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is
also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous
logic, allowing such interrupts to be detected even if the I/O clock is halted. Also, TWI address recognition is
handled in all sleep modes.
6.1.3 Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with
the CPU clock.
General I/O
Modules
CPU Core
RAM
clk
I/O
AVR Clock
Control Unit
clk
CPU
Flash and
EEPROM
clk
FLASH
Source clock
Watchdog TimerReset Logic
Clock
Multiplexer
Watchdog
clock
Calibrated RC
Oscillator
Crystal
Oscillator
External Clock
ADC
clk
ADC
System Clock
Prescaler
Watchdog
Oscillator
USB
clk
USB (48MHz)
PLL Clock
Prescaler
PLL
clk
PllPresc
High Speed
Timer
clk
PLL
PLL Postcaler
(1) (2)
clk
TMR
PLL Input
Multiplexer
Clock Switch